Interconnect structure and method

Abstract

A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductors, and more particularly, to an interconnect structure and a manufacturing method thereof. Background technique [0002] In the current miniaturized semiconductor device process, it is necessary to use low-K value materials as intermetal dielectric layers and / or interlayer dielectric layers between conductive interconnects to reduce resistance and capacitance due to capacitive effects in signal propagation (RC) Delay. Because of this, the lower the dielectric constant of the dielectric, the lower the parasitic capacitance of adjacent conductive lines and the RC delay of the integrated circuit (IC). [0003] However, materials currently considered or used as low-K dielectric materials are not ideal. In particular, when a material is selected based on the K value, and especially based on the material's low K value, other properties, such as hardness or length, may not be ideal for...

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Problems solved by technology

[0003] However, materials currently considered or used as low-K dielectric materials are not ideal

In particular, when selecting a material based on its K value, and especially based on the material's low K value, other properties, such as hardness or length, may not be ideal for use in semiconductor manufacturing processes

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