Programmable gate array based on three-dimensional writable memory (3D-W)

Abstract

The invention discloses a programmable gate array based on a three-dimensional writable memory (3D-W). The programmable gate array includes a programmable computing cell array, a programmable logical cell array and a plurality of programmable connections, wherein each programmable computing cell includes at least one 3D-W array, and the 3D-W array stores a look-up table (LUT) for mathematical functions.

Description

technical field [0001] The present invention relates to the field of integrated circuits, and more specifically, to programmable gate arrays. Background technique [0002] Programmable gate array is a semi-custom integrated circuit, which realizes customization of logic circuits through back-end process or on-site programming. US Patent 4,870,302 discloses a programmable gate array. It contains multiple programmable logic elements (configurable logic element, or configurable logic block) and programmable connections (configurable interconnect, or programmable interconnect). Among them, the programmable logic unit can selectively realize shift, logic not, AND (logic and), OR (logic and), NOR (and not), NAND (and not), XOR (exclusive or) under the control of the setting signal. ), + (arithmetic addition), - (arithmetic subtraction) and other functions; the programmable connection can selectively realize functions such as connection and disconnection between two interconnecti...

AI Technical Summary

Problems solved by technology

Obviously, solidifying computing units will limit the further application of programmable gate arrays

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