Cache performance evaluation method and device

An evaluation device and cache technology, applied in memory systems, instruments, electrical digital data processing, etc., can solve problems such as low accuracy and can not truly reflect the real performance of Cache, and achieve the effect of improving accuracy

Inactive Publication Date: 2017-10-03
SHANGHAI FUDAN MICROELECTRONICS GROUP
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Problems solved by technology

However, the hit rate of the Cache cannot truly reflect the real performance of the Cache, resulting in non-optimal configuration parameters determined according to the evaluation results. lower sex

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  • Cache performance evaluation method and device
  • Cache performance evaluation method and device

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Embodiment Construction

[0049] In practical applications, the application scenarios of embedded SOC are various, and the characteristics of various application scenarios are not the same. It is difficult for a specific structure of Cache to guarantee the versatility between different application scenarios. In addition, the design of embedded SOC not only needs to consider the performance of the system, but also the power consumption, area and cost of the system are also issues that designers need to consider. Therefore, in the Cache design of an embedded SOC, it is usually necessary to evaluate the impact of various structures and parameters on the final Cache acceleration effect under different application requirements.

[0050] However, when using the existing Cache performance evaluation method for Cache performance evaluation, only the Cache hit rate can be obtained according to the simulation process, and the Cache hit rate cannot reflect the real acceleration effect of the Cache, which ultimatel...

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Abstract

The invention discloses a cache performance evaluation method and device. The cache performance evaluation method includes: acquiring memory addresses of n pieces of data to be accessed; adjusting various configuration parameters of a cache to be evaluated, simulating the cache to be evaluated to access the data to be accessed, and acquiring corresponding average access time at different values of various configuration parameters while the data to be accessed is accessed; and using the corresponding average access time at the different values of various configuration parameters as an evaluation result to be output. The cache performance evaluation method and device can improve the accuracy of Cache performance evaluation.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a cache performance evaluation method and device. Background technique [0002] In an embedded system on chip (System On Chip, SOC), a non-volatile memory (Non-Volatile memory, NVM) such as EEPROM or Flash is generally used as a memory for storing instructions. The microprocessor (MCU) completes the function of the system design by reading the instructions in the NVM memory and executing them. [0003] Usually, the execution speed of the MCU is much faster than the reading speed of the NVM, causing the MCU to be often in a waiting state for reading instructions, which makes the speed of reading instructions the bottleneck of the on-chip system, especially the high-performance on-chip storage system. [0004] A mainstream solution to this technical problem is to use an instruction cache (Instruction Cache, Cache for short). By storing the data frequently access...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/0871G06F12/0877G06F12/121
CPCG06F12/0871G06F12/0877G06F12/121
Inventor 沈磊李清张纲俞军陆继承邬佳希张玉花杨皓轩
Owner SHANGHAI FUDAN MICROELECTRONICS GROUP
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