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Sequence pulse falling edge jitter loading apparatus

A technology of sequence pulse and generating device, applied in pulse processing, pulse shaping, pulse technology, etc., to achieve the effect of good scalability and flexibility

Active Publication Date: 2017-10-20
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At present, there is no technology in the domestic public information to add jitter to the sequence pulse signal to test the equipment under test.

Method used

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  • Sequence pulse falling edge jitter loading apparatus
  • Sequence pulse falling edge jitter loading apparatus
  • Sequence pulse falling edge jitter loading apparatus

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0032] figure 1 It is a functional block diagram of a device for adding vibration at the falling edge of a sequence pulse in the present invention.

[0033] In this example, if figure 1 As shown, a device for shaking the falling edge of a sequence pulse in the present invention includes: a data signal generating device, a fan-out circuit, a sharpening circuit 1 and a sharpening circuit 2, a fixed delay circuit 1 and a fixed delay circuit 2, an address controller, Phase shifting circuit, jitter data storage circuit, delay circuit and signal edge synthesis circuit;

[0034] A data signal generating device for generating sequence pulses that need to be dithered and sending them to the fan-out circuit;

[0035] The fan-out circuit is used to fan the sequence pulse into a rising edge signal and a falling edge signal, and then send them to different sharpening circuits respectively;

[0036] The sharpening circuit 1 and the sharpening circuit 2, the sharpening circuit 1 is used t...

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PUM

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Abstract

The invention discloses a sequence pulse falling edge jitter loading apparatus. Waveform decomposition is executed on a sequence pulse needing to load jitter to form a rising edge signal and a falling edge signal, the jitter is converted into delayed timing control, the delayed timing control is loaded to the falling edge, the rising edge signal serves as the clock of a trigger, and the falling edge signal serves as a reset signal, so that the sequence pulse signal is pulled up at the arrival of the rising edge and is pulled down at the arrival of the falling edge, and thus the waveform synthesis of the falling edge jitter loading of the part of sequence pulse signal is realized, wherein the falling edge delays under the action of a programmable delay line, and the numerical value of the delay is program-controlled, so the arrival moment of the falling edge changes with the control data, as the falling edge of the sequence pulse signal synthesized by the rising edge and the falling edge generates periodic jitter, the falling edge can load the programmable jitter r, and thus the expandability and the flexibility are very good.

Description

technical field [0001] The invention belongs to the technical field of digital testing, and more specifically relates to a device for adding vibration to the falling edge of sequence pulses. Background technique [0002] In recent years, under the background of the rapid development of electronic technology, digital equipment has also been continuously developed, and it has shown its uniqueness and shortage in the fields of communication and navigation. Judging from the current situation, the development of digital equipment is accompanied by the development of semiconductor devices, evolving towards integration and intelligence, and presents high precision, high integration, multi-functionality, human-computer interaction, and programmability. characteristics of development. At the same time, the development of semiconductor technology and integration technology has also promoted the innovation of digital technology, and the development of digital technology largely reflec...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K5/06H03K5/133
CPCH03K5/06H03K5/133
Inventor 付在明刘航麟黄建国赵贻玖
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA