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Mask plate, array substrate and manufacturing method thereof

A technology for array substrates and manufacturing methods, which is applied to the photolithographic process of patterned surfaces, semiconductor/solid-state device manufacturing, instruments, etc., can solve the problems of conductive pattern etchant damage and affect product yield, and improve yield Effect

Active Publication Date: 2020-04-21
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, in actual production, since there is no insulating layer covering the conductive pattern in the PAD area, the conductive pattern in the PAD area is exposed. (Anode) during the wet etching (Wet Etch) process, the exposed conductive pattern in the PAD area is easily damaged by the etching solution, thus affecting the product yield

Method used

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  • Mask plate, array substrate and manufacturing method thereof
  • Mask plate, array substrate and manufacturing method thereof
  • Mask plate, array substrate and manufacturing method thereof

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Embodiment Construction

[0049] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention more clear, the following will clearly and completely describe the technical solutions of the embodiments of the present invention in conjunction with the drawings of the embodiments of the present invention. Apparently, the described embodiments are some, not all, embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention belong to the protection scope of the present invention.

[0050] Please refer to figure 1 , the embodiment of the present invention provides a mask 10, the mask 10 is used to form a protective pattern covering at least part of the conductive pattern of the PAD area of ​​the array substrate, the mask 10 includes a light-transmitting area 11 and a The light-transmitting area 12, the opaque area 12 corresponds to at least a partial area of ​​the con...

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Abstract

The invention provides a mask plate, an array substrate and a method for manufacturing the same. The array substrate comprises display regions and PAD regions. The method for manufacturing the array substrate includes forming conductive patterns of the PAD regions; forming protective patterns covering at least partial regions of the conductive patterns; removing the protective patterns after preset film layer patterns of the display regions are formed. The mask plate, the array substrate and the method have the advantages that at least partial regions of the conductive patterns array substrateare protected, accordingly, the conductive patterns can be prevented from being damaged by etching liquid for forming the preset film layer patterns in procedures for forming the preset film layer patterns of the display regions, and the yield of the array substrate can be increased.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a mask plate, an array substrate and a manufacturing method thereof. Background technique [0002] The array substrate usually includes a display area (AA area) and a PAD area, wherein the display area usually includes signal lines such as gate lines and data lines, and components such as thin film transistors (TFT). The PAD area is a crimping area, and is an area for crimping the signal lines of the display area and the leads of the external driving circuit board. Generally, only conductive patterns are provided in the PAD area, and the conductive patterns are used to connect the leads of the external driving circuit board and the signal lines of the array substrate, so the conductive patterns must not be covered by an insulating layer. [0003] However, in actual production, since there is no insulating layer covering the conductive pattern in the PAD area, the conductive pat...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/77H01L27/12G03F1/00
Inventor 张震
Owner BOE TECH GRP CO LTD