Message processing method and device

[0094] The embodiments are described in detail below in conjunction with the drawings in the specification.

[0095] Such as figure 1 As shown, an embodiment of the present invention provides a schematic flowchart of a message processing method, and the method includes the following steps.

[0096] S101: The first network device receives the message at the first time.

[0097] For example, the first network device may be a PTN (Packet Transport Network, packet transport network) device, an OTN (Optical Transport Network, optical transport network) device, a router, or a switch.

[0098] In the embodiment of the present invention, the first time is the time when the first network device receives the message.

[0099] For example, the service carried by the message may be a CPRI service, an SDH service, or a PDH service.

[0100] For example, when the first network device receives the message at the first time, it may record the first time when the message is received.

[0101] For example, when the first network device receives the message at the first time, it may record the first time in a header of the message. The first network device may determine the first time of receiving the message by reading the header of the message.

[0102] For example, when the first network device may also receive the message at the first time, the first time is recorded in the storage medium of the first network device. The first network device may read the first time from the storage medium to determine the time when the message is received.

[0103] For example, the execution subject of S101 may be the receiving circuit in the first network device. The receiving circuit can be used to implement an Ethernet interface.

[0104] S102: The first network device performs processing on the message to obtain a processed message, and writes the processed message to a buffer memory.

[0105] For example, the processing performed by the first network device on the message may be encoding, decoding, encryption or decryption. When the message is an Ethernet frame (ethernet frame), the processing may be to determine the outbound interface for forwarding the message by searching a media access control (MAC) protocol table. When the message is an Internet Protocol (IP) message, the processing may be to determine the outbound interface for forwarding the message by searching a routing table.

[0106] The buffer memory is a memory that stores the processed message. The buffer memory may be a component of the first network device, and may be a memory located inside the first network device. The buffer memory may also be a memory located outside the first network device. The buffer memory may be coupled with the receiving circuit.

[0107] For example, the execution subject of S102 may be the instruction execution circuit in the first network device. The instruction execution circuit may execute the processing on the message according to the instruction. The instruction execution circuit may be implemented by a network processor (NP) or an application-specific integrated circuit (ASIC).

[0108] S103: The first network device reads the processed message from the buffer memory at a second time.

[0109] For example, the execution subject of S103 may be the instruction execution circuit in the first network device.

[0110] S104: The first network device determines the first time delay at which the processed message will reside in the first-in first-out memory at a time after the second time, and the first time delay is equal to the target time The difference obtained by subtracting the second delay from the delay, where the target delay is equal to the period from the first time to the third time at which the processed packet will be forwarded by the first network device through the egress port , The second time delay is equal to the sum of the third time delay and the fourth time delay, the third time delay is equal to the period from the first time to the second time, and the fourth time delay is fixed Time delay, the first-in-first-out memory includes multiple consecutive storage units.

[0111] For example, the multiple consecutive storage units in the FIFO (First In First Out) memory may be used to store a message queue. Each storage unit is used to store a message or null data. The message queue includes at least one message. When the message queue includes multiple messages, the earlier message written by the FIFO memory among the multiple messages is ahead of the multiple messages in the message queue. The position in the message queue of the later message written by the FIFO memory in the text.

[0112] For example, in order to avoid delay jitter when the multiple packets pass through the first network device, the target time delay of each packet in the multiple packets in the first network device Are all equal.

[0113] For example, the value of the target delay may be statically configured by the engineer through the first network device. The target delay may be equal to a fixed value. For example, the engineer configures the target delay for the first network device through telnet. The engineer can determine the target delay for the first network device through experiments. In the case that the first network device does not enable the functions corresponding to S104 to S106, the message used for experiment passing through the first network device will be executed as follows: receiving the data used for experiment through the ingress port Message. The first network device processes the message used for the experiment to obtain the message used for the experiment. Write the processed message for experiment into the buffer memory. Read the processed message for experiment from the buffer memory. Write the processed message for experiment into the FIFO memory. Read the processed message for experiment from the FIFO memory. The processed packet used for experiment is forwarded through the out port. It should be noted that in the foregoing operations, the step of determining the first time delay is not performed. Furthermore, the write pointer used when writing the processed message for experiment into the FIFO memory is not set according to the first delay. The read pointer used when reading the processed message for experiment from the FIFO memory is also not set according to the first delay. The first network device may be capable of processing multiple services. The multiple services correspond to multiple messages respectively. The message used for the experiment may include the multiple messages. For example, the first network device can process service 1, service 2, and service 3. The multiple messages are message 1, message 2, and message 3. Message 1, message 2, and message 3 correspond to business 1, business 2, and business 3, respectively. The time delays for message 1, message 2, and message 3 to pass through the first network device are 3 milliseconds, 4 milliseconds, and 5 milliseconds, respectively. The difference in delays corresponding to different messages is caused by the different time intervals occupied by the first network device processing messages of different services. For example, the time intervals occupied by the first network device to process message 1, message 2, and message 3 are 0.5 milliseconds, 1 millisecond, and 2 milliseconds, respectively. Specifically, the period from when the first network device receives the message 1 through the ingress port to when the first network device writes the processed message 1 into the buffer memory is 0.5 milliseconds. The period from when the first network device receives the message 2 through the ingress port to when the first network device writes the processed message 2 into the buffer memory is 1 millisecond. The period from when the first network device receives the message 3 through the ingress port to when the first network device writes the processed message 3 into the buffer memory is 2 milliseconds.

[0114] The engineer can determine the target delay as the maximum value of the delay for the packet used for the experiment to pass through the first network device, that is, 5 milliseconds, based on the above experiment. Of course, the engineer may also determine the target delay to be a value greater than the maximum value of the delay for the packet used for the experiment to pass through the first network device. For example, the target delay is set to 6 milliseconds, or 7 milliseconds. In this way, after the first network device enables the functions corresponding to S104 to S106, after receiving different messages, it can control the time interval at which different messages reside in the FIFO memory, that is, the first delay , To realize that the delays for different packets to pass through the first network device are all equal to the target delay. For example, the time delay for different packets to pass through the first network device is all equal to 6 milliseconds.

[0115] For example, the target delay of the message in the first network device includes three parts: the first delay, the third delay, and the fourth delay. The first network device may determine that the processed message will be resident in the first time delay in the FIFO memory, so that the message in the first network device The value of the target delay is the statically configured value.

[0116] For example, the first network device may set the read pointer and/or the write pointer of the FIFO memory to determine the first delay for the message to reside in the FIFO memory.

[0117] For example, the third time delay is equal to the difference between the second time and the first time.

[0118] For example, the fourth delay is a fixed delay, which may be determined by the hardware structure of the first network device. Specifically, the buffer memory and the FIFO memory may be connected through a transmission medium. The FIFO memory and the output port may be connected through a transmission medium. After the first network device is created, the transmission medium between the buffer memory and the FIFO memory is determined. In other words, the physical properties of the transmission medium between the buffer memory and the FIFO memory are determined. Therefore, the time interval during which the signal is transmitted on the transmission medium between the buffer memory and the FIFO memory is a fixed value. Similarly, the time interval for signal transmission on the transmission medium between the FIFO memory and the output port is also a fixed value.

[0119] S105: The first network device sets a read pointer and/or a write pointer according to the determined first time delay.

[0120] For example, setting the read pointer may specifically set the value of the read pointer. Setting the write pointer may specifically be setting the value of the write pointer.

[0121] For example, the read pointer of the FIFO memory is used to perform a read operation on the storage unit in the FIFO memory. The write pointer of the FIFO memory is used to perform a write operation on the storage unit in the FIFO memory.

[0122] For example, the first network device may determine the storage unit pointed to by the read pointer according to the first delay, so as to set the value of the read pointer to the address of the storage unit. Alternatively, the first network device may determine the storage unit pointed to by the write pointer according to the first delay, so as to set the value of the write pointer to the address of the storage unit. Alternatively, the first network device may determine the storage unit pointed to by the read pointer and the write pointer according to the first time delay, so as to set the value of the read pointer and the value of the write pointer to the The address of the storage unit.

[0123] S106: The first network device writes the processed message into the storage unit in the first-in-first-out memory according to the set write pointer, or writes the processed message according to the set read pointer. The text is read from the storage unit in the first-in first-out memory.

[0124] For example, after performing a read operation on the storage unit pointed to by the read pointer of the FIFO memory, the read pointer is incremented by 1. The read pointer incremented by 1 points to the next memory cell to be read.

[0125] For example, after performing a write operation on the storage unit pointed to by the write pointer of the FIFO memory, the write pointer is incremented by 1. The write pointer incremented by 1 points to the next memory cell to be written.

[0126] For example, the read operation corresponding to the read pointer and the write operation corresponding to the write pointer can be performed synchronously or asynchronously.

[0127] For example, the first network device performs a write operation on the storage unit according to the set write pointer, so as to write the processed message into the storage unit. The first network device performs a read operation on the storage unit according to the set read pointer to read the processed message from the storage unit.

[0128] S107: The first network device forwards the processed message read from the FIFO memory through the out port at the third time.

[0129] For example, the FIFO memory reads the processed message from the storage unit pointed to by the read pointer by performing a read operation.

[0130] For example, the execution subject of S107 may be the sending circuit in the first network device, and the FIFO memory is a component of the first network device. The sending circuit is coupled with the FIFO memory.

[0131] figure 2 Is provided by the examples figure 1 A schematic diagram of the time delay that occurs when the message passes through the first network device in the method shown. See figure 2 , The message enters the first network device through the ingress port at the first time. The message leaves the first network device through the egress port at the third time. The time delay that occurs when the message passes through the first network device is equal to the target time delay. The target time delay is a period from the first time to the third time. The target delay includes the first delay, the third delay, and the fourth delay.

[0132] The third time delay is equal to the period from the first time to the second time. The first time is the time when the first network device receives the message at the ingress port. The second time is the time for the first network device to read the processed message from the buffer memory. During the period from when the message is received by the ingress port to when the message enters the buffer memory, the first network device processes the message. For example, the first network device may process the message through a network processor (not shown in the figure).

[0133] The first time delay is equal to the period from the time when the processed message is written into the FIFO memory to the time when the processed message is read from the FIFO memory.

[0134] The fourth time delay is a fixed time delay. The fourth time delay includes a first part and a second part. The first part is the period from when the processed message is read from the buffer memory to when the processed message is written into the FIFO memory. The second part is equal to the period from when the processed message is read from the FIFO memory to when the egress port forwards the processed message.

[0135] image 3 It is a schematic flowchart of a message processing method provided by an embodiment of the present invention. See image 3 , The method includes S301 and S302.

[0136] Optionally, figure 1 In the method shown, the first network device setting the write pointer according to the determined first time delay specifically includes:

[0137] S301: The first network device determines the location of the storage unit in the FIFO memory according to the first time delay.

[0138] S302: The first network device sets the write pointer according to the determined location of the storage unit, and the set write pointer points to the storage unit.

[0139] For S301 and S302, please refer to image 3.

[0140] Optionally, image 3 In the method shown, the first network device determining the location of the storage unit in the FIFO memory according to the first time delay specifically includes:

[0141] The first network device determines the location of the storage unit in the FIFO memory according to the following formula:

[0142]

[0143] Wherein, P_add represents the number of storage units spaced between the first storage unit and the second storage unit, the first storage unit and the second storage unit are storage units in the plurality of consecutive storage units, and the The first storage unit is used to store the processed message, the multiple consecutive storage units are used to store the message queue, each storage unit is used to store only one message or idle data, and the second storage The unit is used to store the tail of the message queue, T 1 Indicates the first delay, T read Represents the clock cycle (clock cycle) in which the write pointer performs a write operation on the FIFO memory, Indicates rounding up.

[0144] Optionally, figure 1 In the method shown, the clock frequency (clock frequency) at which the write pointer performs a write operation on the FIFO memory is synchronized with the clock frequency at which the read pointer performs a read operation on the FIFO memory.

[0145] The clock phase of the write pointer performing the write operation to the FIFO memory is synchronized with the clock phase of the read pointer performing the read operation to the FIFO memory.

[0146] The above solution can avoid the unequal rate of data being written when the FIFO memory performs a write operation and the rate of data being read when a read operation is performed. The rate at which data is written is not equal to the rate at which data is read out may cause data loss.

[0147] Optionally, figure 1 In the method shown, S101 may specifically be that the first network device receives the message from the RRU at the first time.

[0148] Optionally, figure 1 In the method shown, S101 may specifically be that the first network device receives the message from the BBU at the first time.

[0149] For example, the first network device is a network device between the BBU and the RRU. The first network device is used to connect the BBU and the RRU. Or, multiple RRUs are connected to one BBU through the first network device. The above solution can avoid that each RRU needs to be directly connected to the BBU through an optical fiber, which helps to save optical fiber and reduce costs. At the same time, when the message passes through the first network device, the delay caused by passing through the first network device is equal to the target delay. The target delay may be equal to a fixed value. When multiple messages pass through the first network device, the first network device may perform similar operations on each message. That is, the first network device may perform operations from S101 to S107 on each message. Therefore, the delay caused by each packet passing through the first network device may be equal to the target delay. Therefore, when the first network device is used to connect the BBU and the RRU, it can be used to forward packets used to carry CPRI services, SDH services, or PDH services. The above scheme can reduce delay jitter.

[0150] According to the method described above, after receiving the message, the first network device determines the first delay for the processed message to reside in the FIFO memory according to the target delay set by the first network device. Make the delay of the message in the first network device equal to the target delay.

[0151] Delay jitter may also occur when multiple packets pass through multiple network devices. In order to avoid delay jitter in the process of multiple packets passing through multiple network devices, the delays that occur when multiple packets pass through multiple network devices may be determined as the same target delay. See the description below for details.

[0152] Figure 4 It is a schematic flowchart of a message processing method provided by an embodiment of the present invention. The method includes the following steps.

[0153] S401: The first network device receives a message from a second network device, where the message carries a first time, and the first time is the time when the second network device receives the message.

[0154] For example, the first network device and the second network device may be PTN devices, OTN devices, routers, or switches.

[0155] For example, an intermediate network device may be included between the first network device and the second network device. That is, the first network device and the second network device may be indirectly connected. The intermediate network device may be a repeater.

[0156] For example, an intermediate network device may not be included between the first network device and the second network device. In other words, the first network device and the second network device may be directly connected. Specifically, the first network device and the second network device may only be connected through a transmission medium. The transmission medium may be a cable or an optical cable.

[0157] In the embodiment of the present invention, the first time is the time when the second network device receives the message.

[0158] For example, the service carried by the message may be a CPRI service, an SDH service, or a PDH service.

[0159] For example, after receiving the message, the second network device may record the first time in the header of the message. The first network device may determine the first time when the second network device receives the message by reading the header of the message.

[0160] For example, the second network device may record the first time in the header of the message through the receiving circuit in the second network device.

[0161] For example, the execution subject of S401 may be the receiving circuit in the first network device. The receiving circuit can be used to implement an Ethernet interface.

[0162] S402: The first network device performs processing on the message to obtain a processed message, and writes the processed message to a buffer memory.

[0163] For example, the processing performed by the first network device on the message may be encoding, decoding, encryption or decryption.

[0164] When the message is an Ethernet frame, the processing may be to determine the outbound interface for forwarding the message by searching the MAC protocol table. When the message is an IP message, the processing may be to determine the outbound interface for forwarding the message by searching a routing table.

[0165] The buffer memory is a memory that stores the processed message. The buffer memory may be a component of the first network device. The buffer memory may be coupled with the receiving circuit.

[0166] For example, the buffer memory may be a memory located inside the first network device, or may be a memory located outside the first network device.

[0167] S403: The first network device reads the processed message from the buffer memory at a second time.

[0168] In S403, the time when the first network device reads the processed message from the buffer memory is the second time.

[0169] For example, the execution subject of S403 may be an instruction execution circuit. The instruction execution circuit may execute the processing on the message according to the instruction. The instruction execution circuit can be implemented by a network processor or an application specific integrated circuit.

[0170] S404: The first network device determines the first time delay at which the processed message will reside in the first-in first-out memory at a time after the second time, and the first time delay is equal to the target time The difference obtained by subtracting the second delay from the delay, where the target delay is equal to the period from the first time to the third time at which the processed packet will be forwarded by the first network device through the egress port , The second time delay is equal to the sum of the third time delay and the fourth time delay, the third time delay is equal to the period from the first time to the second time, and the fourth time delay is fixed Time delay, the first-in-first-out memory includes multiple consecutive storage units.

[0171] For example, the multiple consecutive storage units in the FIFO memory are used to store a message queue, and each storage unit is used to store a message or idle data. The message queue includes at least one message. When the message queue includes multiple messages, the earlier message written by the FIFO memory among the multiple messages is ahead of the multiple messages in the message queue. The position in the message queue of the later message written by the FIFO memory in the text.

[0172] For example, in order to avoid the delay jitter of the multiple packets passing through the second network device and the first network device, the target delay of each packet in the multiple packets is Are the same.

[0173] For example, the value of the target delay is equal to a fixed value. The value of the target delay is statically configured by the engineer through the first network device. The method for configuring the target delay is similar to the description in step S104. For details, please refer to the description in step S104, which will not be repeated here.

[0174] For example, the target delay of the message includes three parts: the first delay, the third delay, and the fourth delay. The first network device determines the first delay for the processed message to be resident in the FIFO memory of the first network device, so that the value of the target delay for the message is the Statically configured value.

[0175] For example, the first network device may set the read pointer and/or write pointer of the FIFO memory to determine the first delay for the message to reside in the FIFO memory in the first network device .

[0176] For example, the third time delay is equal to the difference between the second time and the first time.

[0177] For example, the fourth delay is a fixed delay, which may be determined by the hardware structure of the first network device. Specifically, the buffer memory and the FIFO memory may be connected through a transmission medium. The FIFO memory and the output port may be connected through a transmission medium. After the first network device is created, the transmission medium between the buffer memory and the FIFO memory is determined. In other words, the physical properties of the transmission medium between the buffer memory and the FIFO memory are determined. Therefore, the time interval during which the signal is transmitted on the transmission medium between the buffer memory and the FIFO memory is a fixed value. Similarly, the time interval for signal transmission on the transmission medium connected to the FIFO memory and the output port is also a fixed value.

[0178] S405: The first network device sets a read pointer and/or a write pointer according to the determined first time delay.

[0179] For example, setting the read pointer may specifically set the value of the read pointer. Setting the write pointer may specifically be setting the value of the write pointer.

[0180] For example, the read pointer of the FIFO memory is used to perform a read operation on the storage unit in the FIFO memory. The write pointer of the FIFO memory is used to perform a write operation on the storage unit in the FIFO memory.

[0181] For example, the first network device may determine the storage unit pointed to by the read pointer according to the first delay, so as to set the value of the read pointer to the address of the storage unit. Alternatively, the first network device may determine the storage unit pointed to by the write pointer according to the first delay, so as to set the value of the write pointer to the address of the storage unit. Alternatively, the first network device may determine the storage unit pointed to by the read pointer and the write pointer according to the first time delay, so as to set the value of the read pointer and the value of the write pointer to the The address of the storage unit.

[0182] S406: The first network device writes the processed message to the storage unit in the first-in first-out memory according to the set write pointer, or writes the processed message according to the set read pointer. The text is read from the storage unit in the first-in first-out memory.

[0183] For example, after performing a read operation on the storage unit pointed to by the read pointer of the FIFO memory, the read pointer is incremented by 1. The read pointer incremented by 1 points to the next memory cell to be read.

[0184] For example, after performing a write operation on the storage unit pointed to by the write pointer of the FIFO memory, the write pointer is incremented by 1. The write pointer incremented by 1 points to the next memory cell to be written.

[0185] For example, the read operation corresponding to the read pointer and the write operation corresponding to the write pointer can be performed synchronously or asynchronously.

[0186] For example, the first network device performs a write operation on the storage unit according to the set write pointer, so as to write the processed message into the storage unit. The first network device performs a read operation on the storage unit according to the set read pointer to read the processed message from the storage unit.

[0187] S407: The first network device forwards the processed message read from the first-in-first-out memory at the third time through an egress port.

[0188] For example, the FIFO memory reads the processed message from the storage unit pointed to by the read pointer by performing a read operation.

[0189] For example, the execution subject of S407 may be a sending circuit. Both the sending circuit and the FIFO memory are components of the first network device. The sending circuit is coupled with the FIFO memory.

[0190] Figure 5 Is provided by the examples Figure 4 A schematic diagram of the time delay that occurs when the message passes through the second network device and the first network device in the method shown. See Figure 5 The second network device 501 receives the packet through the ingress port of the second network device 501. After the message is forwarded by the second network device 501, it passes through the bearer network 502 between the second network device 501 and the first network device 500, and is received by the ingress port of the first network device 500 . The target delay is equal to from the first time when the message is received by the second network device 501 at the ingress port to the processed message will be forwarded by the first network device 500 through the egress port The period of the third time. The target delay includes the first delay, the third delay, and the fourth delay.

[0191] The third time delay is equal to the period from the first time to the second time. The first time is the time when the first network device 500 receives the message at the ingress port. The second time is the time for the first network device 500 to read the processed message from the buffer memory. During the period from when the message is received by the ingress port to when the message enters the buffer memory, the first network device processes the message. For example, the first network device may process the message through a network processor (not shown in the figure). In addition, during the period from when the message is received by the ingress port to when the message enters the buffer memory, the second network device or the bearer network 502 may also process the message. It should be noted, Figure 5 , The bearer network 502 is included between the second network device 501 and the first network device 500. During specific implementation, the bearer network 502 may not be included between the second network device 501 and the first network device 500. The second network device 501 and the first network device 500 are connected only through a transmission medium.

[0192] The first time delay is equal to the period from the time when the processed message is written into the FIFO memory to the time when the processed message is read from the FIFO memory.

[0193] The fourth time delay is a fixed time delay. The fourth time delay includes a first part and a second part. The first part is the period from when the processed message is read from the buffer memory to when the processed message is written into the FIFO memory. The second part is equal to the period from when the processed message is read from the FIFO memory to when the processed message is forwarded by the egress port.

[0194] Image 6 It is a schematic flowchart of a message processing method provided by an embodiment of the present invention. See Image 6 , The method includes S601 and S602.

[0195] Optionally, Figure 4 In the method shown, the setting of the write pointer by the first network device according to the first delay specifically includes:

[0196] S601: The first network device determines the location of the storage unit in the FIFO memory according to the first time delay.

[0197] S602: The first network device sets the write pointer to point to the storage unit according to the determined location of the storage unit.

[0198] For S601 and S602, please refer to Image 6.

[0199] Optionally, Image 6 In the method shown, the first network device determining the location of the storage unit in the FIFO memory according to the first time delay specifically includes:

[0200] The first network device determines the location of the storage unit in the FIFO memory according to the following formula:

[0201]

[0202] Wherein, P_add represents the number of storage units spaced between the first storage unit and the second storage unit, the first storage unit and the second storage unit are storage units in the plurality of consecutive storage units, and the The first storage unit is used to store the processed message, the multiple consecutive storage units are used to store the message queue, each storage unit is used to store only one message or idle data, and the second storage The unit is used to store the tail of the message queue, T 1 Indicates the first delay, T read Represents the clock cycle for the write pointer to perform the write operation on the FIFO memory, Indicates rounding up.

[0203] Optionally, Figure 4 In the method shown, the first network device and the second network device adopt a precision time protocol (PTP) or a network time protocol (network time protocol, NTP) for time synchronization.

[0204] The foregoing solution can prevent the reference time point between the first network device and the second network device from being out of synchronization, which causes errors in the calculation of the target delay.

[0205] Optionally, Figure 4 In the method shown, S401 may specifically be that the first network device receives the message from the RRU.

[0206] Optionally, Figure 4 In the method shown, S401 may specifically be that the first network device receives the message from the BBU.

[0207] For example, the first network device is a network device between a BBU and an RRU, and the second network device is a BBU or RRU. The first network device is used to connect the BBU and the RRU. Or, multiple RRUs are connected to the BBU through the first network device. The above solution can avoid that each RRU needs to be directly connected to the BBU through an optical fiber, which helps to save optical fiber and reduce costs. At the same time, when the message passes through the first network device, the delay generated by the second network device and the first network device is equal to the target delay, and the target delay may be equal to a fixed value . When multiple packets pass through the second network device and the first network device, the first network device may perform similar operations on each packet. That is, the first network device may perform operations from S401 to S407 on each message. Therefore, when the first network device is used to connect the BBU and the RRU, it can be used to forward packets used to carry CPRI services, SDH services, or PDH services. The above scheme can reduce delay jitter.

[0208] According to the method described above, after the first network device receives the message, according to the target delay set by the first network device or the second network device, it is determined that the processed message resides in the FIFO memory of the first network device The first delay of the message between the second network device and the first network device is equal to the preset target delay, thereby preventing the message from being transmitted between the second network device and the first network device , Storage, forwarding, and switching processing.

[0209] Based on the same inventive concept as the above method, an embodiment of the present invention also provides a message processing device.

[0210] Figure 7 It is a schematic structural diagram of a message processing apparatus provided by an embodiment of the present invention. The message processing device 700 can be used to execute figure 1 The method shown. For example, the message processing apparatus 700 may be a PTN device, an OTN device, a router or a switch.

[0211] See Figure 7 , The message processing device 700 includes: a receiving unit 701, a processing unit 702, a reading unit 703, a first delay determining unit 704, a setting unit 705, and a forwarding unit 706.

[0212] The receiving unit 701 is configured to receive a message at the first time.

[0213] The receiving unit 701 may be used to perform S101. For the function and specific implementation of the receiving unit 701, please refer to figure 1 The description of S101 in the embodiment corresponding to the shown method will not be repeated here.

[0214] The processing unit 702 is configured to perform processing on the message received by the receiving unit 701 to obtain a processed message, and write the processed message to the buffer memory.

[0215] The processing unit 702 may be used to perform S102. For the function and specific implementation of the processing unit 502, please refer to figure 1 The description of S102 in the embodiment corresponding to the shown method will not be repeated here.

[0216] The reading unit 703 is configured to read the processed message obtained by the processing unit 702 from the buffer memory at a second time.

[0217] The reading unit 703 may be used to perform S103. For the function and specific implementation of the reading unit 703, please refer to figure 1 The description of S103 in the embodiment corresponding to the method shown is not repeated here.

[0218] The first delay determining unit 704 is configured to determine the first delay at which the processed message read by the reading unit 703 will reside in the FIFO memory at a time after the second time, and the first delay The first delay is equal to the difference obtained by subtracting the second delay from the target delay, and the target delay is equal to the third time from the first time until the processed packet will be forwarded by the forwarding unit 706 through the egress port. The second time delay is equal to the sum of the third time delay and the fourth time delay, the third time delay is equal to the period from the first time to the second time, and the fourth time The delay is a fixed delay, and the FIFO memory includes a plurality of continuous storage units.

[0219] The first delay determining unit 704 may be used to perform S104. For the function and specific implementation of the first delay determining unit 704, please refer to figure 1 The description of S104 in the embodiment corresponding to the shown method will not be repeated here.

[0220] The setting unit 705 is configured to set a read pointer and/or a write pointer according to the first delay determined by the first delay determining unit 704. The processed message is written into the storage unit in the FIFO memory according to the set write pointer. Or, read the processed message from the storage unit in the FIFO memory according to the set read pointer.

[0221] The setting unit 705 may be used to execute S105. For the function and specific implementation of the setting unit 705, please refer to figure 1 The description of S105 in the embodiment corresponding to the shown method will not be repeated here.

[0222] The forwarding unit 706 is configured to forward the processed message read from the FIFO memory through the out port at the third time.

[0223] The forwarding unit 706 can be used to perform S106. For the function and specific implementation of the forwarding unit 706, please refer to figure 1 The description of S106 in the embodiment corresponding to the shown method will not be repeated here.

[0224] Optionally, the setting unit 705 is specifically configured to:

[0225] Determine the location of the storage unit in the FIFO memory according to the first time delay;

[0226] The write pointer is set according to the determined location of the storage unit, and the set write pointer points to the storage unit.

[0227] Optionally, the setting unit 705 is specifically configured to:

[0228] Determine the location of the storage unit in the FIFO memory according to the following formula:

[0229]

[0230] Wherein, P_add represents the number of storage units spaced between the first storage unit and the second storage unit, the first storage unit and the second storage unit are storage units in the plurality of consecutive storage units, and the The first storage unit is used to store the processed message, the multiple consecutive storage units are used to store the message queue, each storage unit is used to store only one message or idle data, and the second storage The unit is used to store the tail of the message queue, T 1 Indicates the first delay, T read Represents the clock cycle for the write pointer to perform the write operation on the FIFO memory, Indicates rounding up.

[0231] Optionally, the clock frequency at which the write pointer performs a write operation on the FIFO memory is synchronized with a clock frequency at which the read pointer performs a read operation on the FIFO memory.

[0232] The phase of the clock when the write pointer performs a write operation on the FIFO memory is synchronized with the phase of a clock when the read pointer performs a read operation on the FIFO memory.

[0233] Optionally, the receiving unit 701 is specifically configured to:

[0234] Receive the message from the RRU at the first time.

[0235] Optionally, the receiving unit 701 is specifically configured to:

[0236] Receive the message from the BBU at the first time.

[0237] Based on the same inventive concept as the above method, an embodiment of the present invention also provides a message processing device.

[0238] Picture 8 It is a schematic structural diagram of a message processing apparatus provided by an embodiment of the present invention. The message processing device 800 can be used to execute Figure 4 The method shown. For example, the message processing apparatus 800 may be a PTN device, an OTN device, a router or a switch.

[0239] See Picture 8 , The message processing apparatus 800 includes: a receiving unit 801, a processing unit 802, a reading unit 803, a first delay determining unit 804, a setting unit 805, and a forwarding unit 806.

[0240] The receiving unit 801 is configured to receive a message from the second network device. The message carries a first time, and the first time is the time when the second network device receives the message.

[0241] For example, the receiving unit 801 may be used to perform S401. For the function and specific implementation of the receiving unit 801, please refer to Figure 4 The description of S401 in the embodiment corresponding to the shown method will not be repeated here.

[0242] The processing unit 802 is configured to perform processing on the message received by the receiving unit 801 to obtain a processed message, and write the processed message to the buffer memory.

[0243] For example, the processing unit 802 may be used to perform S402. For the function and specific implementation of the processing unit 802, please refer to Figure 4 The description of S402 in the embodiment corresponding to the shown method will not be repeated here.

[0244] The reading unit 803 is configured to read the processed message obtained by the processing unit 802 from the buffer memory at a second time.

[0245] For example, the reading unit 803 may be used to perform S403. For the function and specific implementation of the reading unit 803, please refer to Figure 4 The description of S403 in the embodiment corresponding to the shown method will not be repeated here.

[0246] The first time delay determining unit 804 is configured to determine the first time delay at which the processed message read by the reading unit 803 will be resident in the first-in first-out FIFO memory at a time after the second time. The first delay is equal to the difference obtained by subtracting the second delay from the target delay. The target delay is equal to the period from the first time to the third time at which the processed packet will be forwarded by the forwarding unit through the outgoing port. The second delay is equal to the sum of the third delay and the fourth delay. The third time delay is equal to the period from the first time to the second time. The fourth time delay is a fixed time delay, and the FIFO memory includes a plurality of continuous storage units.

[0247] For example, the first delay determining unit 804 may be used to perform S404. For the function and specific implementation of the first delay determining unit 804, please refer to Figure 4 The description of S404 in the embodiment corresponding to the shown method will not be repeated here.

[0248] The setting unit 805 is configured to set a read pointer and/or a write pointer according to the first delay determined by the first delay determining unit 804; write the processed message into the FIFO memory according to the set write pointer Or, read the processed message from the storage unit in the FIFO memory according to the set read pointer.

[0249] For example, the setting unit 805 may be used to execute S405. For the function and specific implementation of the setting unit 805, please refer to Figure 4 The description of S405 in the embodiment corresponding to the shown method will not be repeated here.

[0250] The forwarding unit 806 is configured to forward the processed message read from the FIFO memory through the out port at the third time.

[0251] For example, the forwarding unit 806 may be used to perform S406. For the function and specific implementation of the forwarding unit 806, please refer to Figure 4 The description of S406 in the embodiment corresponding to the shown method will not be repeated here.

[0252] Optionally, the setting unit 805 is specifically configured to:

[0253] The first network device determines the location of the storage unit in the FIFO memory according to the first time delay.

[0254] The first network device sets the write pointer to point to the storage unit according to the determined location of the storage unit.

[0255] Optionally, the setting unit 805 is specifically configured to:

[0256] Determine the location of the storage unit in the FIFO memory according to the following formula:

[0257]

[0258] Wherein, P_add represents the number of storage units spaced between the first storage unit and the second storage unit, the first storage unit and the second storage unit are storage units in the plurality of consecutive storage units, and the The first storage unit is used to store the processed message, the multiple consecutive storage units are used to store the message queue, each storage unit is used to store only one message or idle data, and the second storage The unit is used to store the tail of the message queue, T 1 Indicates the first delay, T read Represents the clock cycle for the write pointer to perform the write operation on the FIFO memory, Indicates rounding up.

[0259] Optionally, a precise clock synchronization protocol or a network time protocol is used between the apparatus and the second network device for time synchronization.

[0260] Optionally, the receiving unit 801 is specifically configured to:

[0261] Receive the message from the RRU.

[0262] Optionally, the receiving unit 801 is specifically configured to:

[0263] Receive the message from the BBU.

[0264] Based on the same inventive concept as the above method, the embodiment of the present invention also provides a network device.

[0265] Picture 9 This is a schematic structural diagram of a network device provided by an embodiment of the present invention. For example, the network device 900 may be a PTN device, an OTN device, a router, or a switch.

[0266] See Picture 9 , The network device 900 includes: a receiving circuit 901, a buffer memory 902, a FIFO memory 903, an instruction execution circuit 904, a sending circuit 905, and an instruction memory 906.

[0267] The instruction execution circuit 904 and the instruction memory 906 are coupled. The instruction memory 906 is used to store computer instructions. The instruction execution circuit 904 realizes functions by reading the computer instructions. For example, the instruction execution circuit 904 implements processing of messages.

[0268] The instruction execution circuit 904 is respectively coupled with the receiving circuit 901, the buffer memory 902, the FIFO memory 903, the instruction execution circuit 904, and the sending circuit 905. Specifically, the instruction execution circuit 904 can obtain the data received by the receiving circuit 901 by performing a read operation on the receiving circuit 901. The instruction execution circuit 904 can provide data to the transmission circuit 905 by performing a write operation on the transmission circuit 905. The instruction execution circuit 904 can perform a read operation and a write operation on the buffer memory 902. The instruction execution circuit 904 can perform a read operation and a write operation on the FIFO memory 903. The output terminal of the receiving circuit 901 is coupled with the input terminal of the buffer memory 902. The buffer memory 902 can receive data sent by the receiving circuit 901. The output terminal of the buffer memory 902 is coupled with the input terminal of the FIFO memory 903. The FIFO memory 903 can receive the data sent by the buffer memory 902. The output terminal of the FIFO memory 903 is coupled with the input terminal of the transmitting circuit 905. The transmitting circuit 905 can receive the data transmitted by the FIFO memory 903. The network device 900 can be used to perform figure 1 The method shown. The receiving circuit 901 can be used to perform S101.

[0269] The instruction execution circuit 904 can execute S102 by accessing the computer program in the instruction memory 906, and read the processed message by accessing the buffer memory 902. The instruction execution circuit 904 can execute S103 by accessing the computer program in the instruction memory 906.

[0270] The instruction execution circuit 904 can execute S104 by accessing the computer program in the instruction memory 906.

[0271] The instruction execution circuit 904 can execute S105 by accessing a computer program in the instruction memory 906, and execute a write and/or read operation on the FIFO memory 903 through a write pointer and/or a read pointer. The instruction execution circuit 904 can execute S106 by accessing the computer program in the instruction memory 906.

[0272] The sending circuit 905 can be used to perform S107. Specifically, the sending circuit 905 may be used to implement the outgoing port involved in S107.

[0273] The network device 900 can be used to perform Figure 4 The method shown. The receiving circuit 901 can be used to perform S401.

[0274] The instruction execution circuit 904 can execute S402 by accessing the computer program in the instruction memory 906, and read the processed message by accessing the buffer memory 902. The instruction execution circuit 904 can execute S403 by accessing the computer program in the instruction memory 906.

[0275] The instruction execution circuit 904 can execute S404 by accessing the computer program in the instruction memory 906.

[0276] The instruction execution circuit 904 can execute S405 by accessing a computer program in the instruction memory 906, and execute a write and/or read operation on the FIFO memory 903 through a write pointer and/or a read pointer. The instruction execution circuit 904 can execute S406 by accessing the computer program in the instruction memory 906.

[0277] The sending circuit 905 can be used to perform S407. Specifically, the sending circuit 905 may be used to implement the outgoing port involved in S407.

[0278] Picture 10 This is a schematic structural diagram of a network device provided by an embodiment of the present invention. For example, the network device 1000 may be a PTN device, OTN device, router or switch.

[0279] See Picture 10 , The network device 1000 includes: an ingress port 1001, an egress port 1002, a logic circuit 1003, and a memory 1004. The logic circuit 1003 is coupled with the input port 1001, the output port 1002, and the memory 1004 through a bus. The memory 1004 stores computer programs. The logic circuit 1003 can realize functions by executing the memory 1004 to store a computer program. For example, the logic circuit 1003 implements processing of messages.

[0280] The network device 1000 can be used to perform figure 1 The method shown. The network device 1000 can be used to implement figure 1 The method shown involves the first network device. The ingress port 1001 can be used to execute S101. The logic circuit 1003 can execute S102 by accessing a computer program in the memory 1004. The memory 1004 may be used to implement the buffer memory involved in S102.

[0281] The logic circuit 1003 can execute S103 by accessing the computer program in the memory 1004. The logic circuit 1003 can execute S104 by accessing the computer program in the memory 1004. In addition, the memory 1004 may be used to implement the FIFO memory involved in S104.

[0282] The logic circuit 1003 can execute S105 by accessing the computer program in the memory 1004. The logic circuit 1003 can execute S106 by accessing the computer program in the memory 1004.

[0283] Outgoing port 1002 can be used to execute S1010. Specifically, the egress port 1002 may be used to implement the egress port involved in S107.

[0284] The network device 1000 can be used to perform Figure 4 The method shown. The network device 1000 can be used to implement Figure 4 The method shown involves the first network device. The ingress port 1001 can be used to execute S401. The logic circuit 1003 can execute S402 by accessing the computer program in the memory 1004. The memory 1004 may be used to implement the buffer memory involved in S402.

[0285] The logic circuit 1003 can execute S403 by accessing the computer program in the memory 1004. The logic circuit 1003 can execute S404 by accessing the computer program in the memory 1004. In addition, the memory 1004 may be used to implement the FIFO memory involved in S404.

[0286] The logic circuit 1003 can execute S405 by accessing the computer program in the memory 1004. The logic circuit 1003 can execute S406 by accessing the computer program in the memory 1004.

[0287] The egress port 1002 can be used to execute S407. Specifically, the egress port 1002 may be used to implement the egress port involved in S407.

[0288] Those skilled in the art should understand that the embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may be in the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, optical storage, etc.) containing computer-usable program codes.

[0289] The present invention is described with reference to flowcharts and/or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and/or block in the flowchart and/or block diagram, and the combination of processes and/or blocks in the flowchart and/or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing equipment to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing equipment are generated In the process Figure one Process or multiple processes and/or boxes Figure one A device with functions specified in a block or multiple blocks.

[0290] These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing equipment to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction device. The device is implemented in the process Figure one Process or multiple processes and/or boxes Figure one Function specified in a box or multiple boxes.

[0291] These computer program instructions can also be loaded on a computer or other programmable data processing equipment, so that a series of operation steps are executed on the computer or other programmable equipment to produce computer-implemented processing, so as to execute on the computer or other programmable equipment. Instructions are provided to implement the process Figure one Process or multiple processes and/or boxes Figure one Steps of functions specified in a box or multiple boxes.

[0292] Those skilled in the art can make changes and modifications to the technical solutions provided in the embodiments of the present invention. If these modifications and variations fall within the scope of the equivalent technical solutions of the claims of the present invention, the above-mentioned modifications and variations also belong to the protection scope of the present invention.