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Memory device with input circuit and method of operating the memory device

A technology of input circuit and operation method, which is applied in the direction of static memory, digital memory information, information storage, etc., and can solve problems such as difficult to meet input setting and storage time requirements

Active Publication Date: 2020-09-01
WINBOND ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as data transfer speeds become faster, it becomes more difficult to meet input set and save time requirements

Method used

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  • Memory device with input circuit and method of operating the memory device
  • Memory device with input circuit and method of operating the memory device
  • Memory device with input circuit and method of operating the memory device

Examples

Experimental program
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Embodiment Construction

[0059] Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

[0060] figure 1 The memory system 100 will be described. The memory system 100 includes a controller 110 and a memory device 120 coupled to the controller 110 . The memory device 120 includes an input circuit 130 , a memory cell array 150 and a test pattern generator 160 . The input circuit 130 includes an input receiver 131 (in figure 1 Indicated as "INPUT RCV"), internal input delay circuit 132, trimming circuit 133 (in figure 1 Indicated as "tIS / tlH trim"), input driver 134, clock receiver 135 (in figure 1 Indicated as "CLK RCV"), internal clock delay circuit 136, clock driver 137 and data latch 138 (in figure 1 denoted as “F / F” in ), the data latch 138 is coupled to receive the output of the input driver 134 a...

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PUM

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Abstract

The invention proposes an input circuit of a memory device. The input circuit of the memory device includes an input receiver for receiving an input signal, a clock receiver for receiving a clock signal, a data latch, an input signal delay path coupled to the input receiver and configured to provide a delayed internal input signal to the data latch , a first clock signal delay path coupled to the clock receiver and configured to provide a first delayed internal clock signal, a second clock signal delay path coupled to the input receiver and configured to provide a second delayed internal clock signal, and multiplexing The register is coupled to receive and select one of the first delayed internal clock signal and the second delayed internal clock signal and to provide the selected signal to the data latch in response to the test mode control signal.

Description

technical field [0001] The present invention relates to a memory device, in particular to a memory device with an input circuit and an operating method of the memory device. Background technique [0002] Memory devices are included in computers or other electronic devices used to store data. Typically, data to be stored in a memory device is buffered in an input circuit of the memory device. In order for the input circuit to properly capture data, the signals in the input circuit must meet the input setup and hold time requirements. However, as data transfer speeds become faster, it becomes more difficult to meet input setup and storage time requirements. Contents of the invention [0003] The invention provides a memory system, an input circuit of a memory device and an operation method thereof. [0004] According to an embodiment of the present invention, an input circuit of a memory device comprises: an input receiver for receiving an input signal; a clock receiver f...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C7/22
CPCG11C7/22G11C7/1084G11C7/1093G11C7/222G11C7/225G11C2207/2254G11C29/12015G11C29/56012G11C29/023G11C29/028G11C7/1006G11C29/02G11C7/1051
Inventor 崔明灿
Owner WINBOND ELECTRONICS CORP