Memory device with input circuit and method of operating the memory device
A technology of input circuit and operation method, which is applied in the direction of static memory, digital memory information, information storage, etc., and can solve problems such as difficult to meet input setting and storage time requirements
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[0059] Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
[0060] figure 1 The memory system 100 will be described. The memory system 100 includes a controller 110 and a memory device 120 coupled to the controller 110 . The memory device 120 includes an input circuit 130 , a memory cell array 150 and a test pattern generator 160 . The input circuit 130 includes an input receiver 131 (in figure 1 Indicated as "INPUT RCV"), internal input delay circuit 132, trimming circuit 133 (in figure 1 Indicated as "tIS / tlH trim"), input driver 134, clock receiver 135 (in figure 1 Indicated as "CLK RCV"), internal clock delay circuit 136, clock driver 137 and data latch 138 (in figure 1 denoted as “F / F” in ), the data latch 138 is coupled to receive the output of the input driver 134 a...
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