Error Correction Code and Read Adjustment Based on Dynamic Memory Error Model Estimation

An error model and memory technology, applied in the field of error correction code input data, can solve problems such as no improvement of soft bits and reduced decoding ability of LDPC decoders

An error model and memory technology, applied in the field of error correction code input data, can solve problems such as no improvement of soft bits and reduced decoding ability of LDPC decoders

CN108153608BActive Publication Date: 2021-06-15SANDISK TECH LLC
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  • Error Correction Code and Read Adjustment Based on Dynamic Memory Error Model Estimation
  • Error Correction Code and Read Adjustment Based on Dynamic Memory Error Model Estimation
  • Error Correction Code and Read Adjustment Based on Dynamic Memory Error Model Estimation

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[0029] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS will be described with reference to the drawings. In the specification, common reference numerals in the various figures denote common features. As used herein, ordinal words (e.g., "first," "second," "third," etc.) used to modify an element such as a structure, component, operation, etc., do not by themselves indicate the relative Any precedence or order, but just to distinguish an element from another element with the same name (used instead for ordinal numbers).

[0030] The present disclosure describes systems, devices, and methods for adjusting decode parameters or read parameters based on estimates of memory error models. A memory error model is defined by a set of error counts corresponding to different "reliability bins" or "voltage bins". Each reliability bin or voltage bin can be determined by reading a combination of hard and soft bits. The set of error counts may specify the expected number of erroneous bi...

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Abstract

An apparatus includes a memory and a controller coupled to the memory. The controller is configured to determine a first count of bits in the data representation that are estimated to be erroneous and a second count of bits in the data representation that are estimated to be erroneous with a high estimation reliability. The controller is also configured to modify at least one read parameter or at least one decode parameter based on the first count and the second count.

Description

technical field [0001] The present disclosure relates to error correcting code (ECC) input data. Background technique [0002] Non-volatile data storage devices, such as embedded flash memory, have enabled increased portability of data and software applications. Information read from a non-volatile data storage device is typically processed by an error correcting code (ECC: error correct code) decoder to correct mistake. An example of such an ECC decoder is a Low Density Parity Check (LDPC) decoder. [0003] An LDPC decoder may use soft bits (eg, reliability information) to decode hard bits (eg, information indicating a voltage read from a memory). Utilizing the reliability information (soft bits) can significantly improve the correction capability of the decoder. Soft bits may indicate the reliability of the corresponding hard bits. For example, the value of a soft bit may indicate a low reliability value if the corresponding voltage read from the storage element is ne...

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Application Information

Patent Timeline
15 Jun 2021
Publication
CN108153608B
IPC
G06F11/10
CPC
G06F11/1044; H03M13/1111; H03M13/3715; H03M13/3723; H03M13/6325; G06F11/1012; G06F3/0619; G06F3/065
Inventors
E.沙伦; A.巴扎尔斯基