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Memory device with cell over periphery structure and memory package comprising same

A technology of storage devices and peripheral circuits, applied in the field of memory packaging

Active Publication Date: 2018-07-31
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, the reduction in size of vertical memory devices is limited because the memory devices must still include interfaces to electrically connect the memory devices to peripheral circuits for communicating with and being driven by external devices

Method used

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  • Memory device with cell over periphery structure and memory package comprising same
  • Memory device with cell over periphery structure and memory package comprising same
  • Memory device with cell over periphery structure and memory package comprising same

Examples

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Embodiment Construction

[0025] Exemplary embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. However, this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

[0026] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. figure 1 is a perspective view of a memory device according to an exemplary embodiment of the inventive concept.

[0027] exist figure 1 In , the direction substantially perpendicular to the first surface (eg, top surface) of the substrate is referred to as a first direction D1 (eg, Z-axis direction). Also, two directions substantially parallel to the first surface of the substrate and intersecting each other are referred to as a second direction D2 (eg, X-axis direction) and a thi...

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Abstract

The invention provides a memory device with a cell over periphery structure and a memory package comprising the same. The memory device comprises a substrate and a peripheral circuit arranged on the first surface of the substrate, wherein the peripheral circuit comprises a first transistor. The memory device also comprises a first wiring layer arranged on the peripheral circuit, a base layer arranged on the first wiring layer, a memory unit array arranged on the base layer and a second wiring layer arranged on the memory unit array, wherein the second wiring layer comprises first power wiringconfigured to supply first voltage, second power wiring configured to supply second voltage and first wiring electrically connected with the first transistor; and the first wiring is configured to beelectrically connected with the first power wiring or the second power wiring.

Description

technical field [0001] Example embodiments of inventive concepts relate generally to memory devices, and more particularly, to memory devices having a cell over periphery (COP) structure and memory packages including the same. Background technique [0002] A vertical memory device, commonly referred to as a three-dimensional (3D) memory device, is a memory device including a plurality of memory cells repeatedly stacked on a surface of a substrate. These memory devices are capable of very high storage capacities in very small structures. For example, in a vertical memory device, a channel may protrude from a surface of a substrate or may extend vertically from the surface of the substrate, and gate lines and insulating layers surrounding the vertical channel may be repeatedly stacked. [0003] However, reduction in size of vertical memory devices is limited because the memory devices must still include interfaces to electrically connect the memory devices to peripheral circu...

Claims

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Application Information

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IPC IPC(8): H01L27/11529H01L27/11573H10B41/41H10B43/40
CPCH10B41/41H10B43/40
Inventor 金昶汎金成勋
Owner SAMSUNG ELECTRONICS CO LTD
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