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Partition alignment method of via hole layers and circuit pattern layers

A circuit pattern and via hole technology, applied in printed circuits, printed circuit manufacturing, electrical components, etc., can solve the problems of low contrast accuracy and high alignment accuracy, achieve high alignment accuracy and solve alignment problems.

Active Publication Date: 2018-09-14
JIANGSU BOMIN ELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the inconsistency between the expansion and contraction ratio of the via hole layer and the circuit layer (the PCB board will change in size due to temperature changes during the production process), the existing alignment processing method of the panel is adopted, and the alignment of the PCB board is completed. Finally, there are the following significant defects: the alignment accuracy of PCB items near the center of the PCB panel is high (good product), while the contrast accuracy of PCB items near the edge of the PCB panel is very low (waste).

Method used

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  • Partition alignment method of via hole layers and circuit pattern layers
  • Partition alignment method of via hole layers and circuit pattern layers
  • Partition alignment method of via hole layers and circuit pattern layers

Examples

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Embodiment 1

[0043] For the convenience of description, we take a PCB puzzle composed of four PCB units as an embodiment 1 of the present invention, as Image 6 As shown: in the first embodiment, there are four PCB shipping units (P1, P2, P3, P4) with the same size designed on the PCB board. The sizes of the four shipping units are all a*b, and the four shipping units The center points of the units are M1, M2, M3, M4 respectively. The area on the PCB panel except for the four PCB shipping units (P1, P2, P3, P4) is the frame area.

[0044] continue to refer Image 6 As shown, in this embodiment, the partition alignment method of the via hole layer and the circuit pattern layer provided by the present invention includes the following steps:

[0045]Step 1. Design four partition center positioning targets (A1, A2, A3, A4) and four partition graphics expansion and contraction targets (B1, B2, B3, B4) at the four corners of the border of the PCB panel, and the center The preset expansion and...

Embodiment 2

[0055] In order to further describe the technical solution of the present invention, embodiment two provides a kind of four-layer PCB board (such as Figure 7 Shown) processing technology, this processing technology has used the partition alignment method of the present invention.

[0056] Such as Figure 8 As shown, in Example 2, the overall size of the PCB panel is 500mm*600mm, and the PCB panel is designed with 8 PCB shipping units of the same size, and the size of the 8 shipping units is 150mm*100mm, 8 The center points of each shipping unit are respectively M1, M2, M3, M4, M5, M6, M7, and M8. The area on the PCB panel except for the 8 PCB shipping units is the frame area.

[0057] Establish a coordinate system with the center of the PCB panel as the origin, where: the orientation angles of the three PCB shipment units on the left (representing the angle between the long side and the X axis) are 0°, and the orientation angles of the two middle PCB shipment units They ar...

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PUM

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Abstract

The invention discloses a partition alignment method of via hole layers and circuit pattern layers. The method comprises the following steps: forming a rectangular PCB jointed board, ensuring that a plurality of PCB shipment units with the same sizes are distributed on the PCB jointed board, and ensuring that the area outside the positions of the PCB shipment units on the PCB jointed board servesas a border area; respectively designing a plurality of partition center positioning targets and partition pattern positioning targets on the edge of the border area; obtaining coordinate values of all the partition center positioning targets and partition pattern positioning targets before expansion and contraction; machining the PCB jointed board; obtaining coordinate values of center points ofall the shipment units after expansion and contraction; obtaining sizes of all the shipment units after expansion and contraction; generating program data of a plurality of via hole layers forming one-to-one correspondence with all the shipment units; and machining all the via hole layers onto the PCB jointed board in an alignment manner according to the program data of the via hole layers.

Description

technical field [0001] The invention belongs to the field of printed circuit board manufacturing, and more specifically relates to a partition alignment method for a via hole layer and a circuit pattern layer. Background technique [0002] With the development of science and technology, the functions of electronic products are becoming more and more abundant, so the requirements for the refinement of printed circuit boards (PCBs) are also getting higher and higher. Such as figure 1 As shown, the PCB generally includes a via layer (laser-processed hole layer H2 and mechanically-processed hole layer H1 that are conductive after copper plating) and a circuit layer. The alignment accuracy of the via layer and the circuit layer directly determines the PCB Board product performance. Therefore, major PCB board manufacturers have invested a lot of manpower and material resources to improve the alignment process level between the via hole layer and the circuit layer. [0003] On t...

Claims

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Application Information

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IPC IPC(8): H05K3/00
CPCH05K3/0047H05K2203/166
Inventor 徐缓刘东虎
Owner JIANGSU BOMIN ELECTRONICS
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