This invention discloses a planar gate SiC
MOSFET device and its fabrication method. The fabrication method includes: depositing a first
silicon oxide layer in a substrate; forming an N+ source region injection window
mask through
photolithography, development, and
etching; covering the surface of the first
silicon oxide layer above the P-type region with a first
nitride layer; depositing a second
silicon oxide layer, a second
nitride layer, and a second polysilicon layer; using the second
nitride layer as a
barrier layer to planarize the second polysilicon layer; and sequentially
etching away the second nitride layer, the second
silicon oxide layer, the first nitride layer, and the first
silicon oxide layer above the P-type region to form a P+ injection window. This application, by changing the process steps, eliminates the need for a P+
mask, enabling self-alignment of N+ and P+ processes. It also avoids
mask alignment problems caused by
wafer warpage, reduces registration deviation, improves the accuracy of the injection window region, saves costs, and allows for smaller
cell sizes and optimized specific on-resistance.