Width adjustment type self-excitation quantization register of quantification logic

Abstract

The invention discloses a width adjustment type self-excitation quantization register of quantification logic. The width adjustment type self-excitation quantization register consists of a basic unitcircuit, a queue circuit and a full-value quantization circuit, wherein the emitting electrode nodes of audions on two ends of the queue circuit (n) are independently connected with audions Tc and Td,the emitting electrode of the audion Tc is coupled and connected with the emitting electrode of the unit audion 2 of one end of a queue through Ie, and the emitting electrode of the audion Td is coupled and connected with the emitting electrode of the unit audion 1 (n) of one end of the queue through Ie; and the collector electrodes of all audions 1 in the queue (n) are connected with the collector electrode of the audion Tc to form a node G, the collector electrodes of all audions 2 in the queue (n) are connected with the collector electrode of the audion Td to form a node V, the base electrodes of all audions 1 in the queue (n) are connected with the base electrode of the Tc to form a read-write side node, and the base electrodes of all audions 2 in the queue (n) are connected to distribution nodes Bh0, Bh1, Bh2...Bhn in a threshold voltage generation circuit in sequence according to a serial number.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to the realization of one of the basic hardware of multi-valued computer "quantization logic self-excited quantization register of widening adjustable current type" technical background [0002] So far all computers and their related digital systems are binary. Although multi-valued computing has many advantages, it develops very slowly because there is no key hardware supporting multi-valued computing. It can be said that multi-valued computers, especially decimal The realization of the computer is almost zero. In view of this situation, I have proposed a simple and effective multi-valued calculation implementation circuit, especially an effective method for ten-valued calculations and the addition and subtraction of multi-valued, especially ten-valued, implementations with binary hardware. , multiplication, and division arithmetic operations and key circuits of logic ope...

AI Technical Summary

Problems solved by technology

[0002] So far all computers and their related digital systems are binary. Although multi-valued computing has many advantages, it develops very slowly because there is no key hardware supporting multi-valued computing. It can be said that multi-valued computers, especially decimal The realization of the computer is almost zero. In view of this situation, I have proposed a simple and effective multi-valued calculation implementation circuit, especially an effective method for ten-valued calculations and the addition and subtraction of multi-valued, especially ten-valued, implementations with binary hardware. , multiplication, and division arithmetic operations and key circuits of logic operations, which are called "quantization logic" and its circuits. For details, refer to the patent application (201710023530.1201710023529.9201710023528.4201710024248.5201710024246.6201710024247.0). The quantization logic itself has two information modes, one One is the bit weight information mode, and the other is the width weight information mode. The specific circuits in the two information modes are also quite different. In actual work, the bit weight information and the width weight information are converted to each other. The numerical operation of value information depends on bit weight information, but the performance of natural information is mostly analog information, so obtaining standard bit weight and amplitude weight information will be the key to the actual application of the circuit, and the multi-valued storage method of amplitude weight information is also what we expected

Images