Multi-value amplitude weight variable compensation device of quantification logic

Abstract

The invention provides a multi-value amplitude weight variable compensation device of quantification logic. The multi-value amplitude weight variable compensation device is composed of an n-value bitweight quantizer and an n-value amplitude weight quantizer, and is characterized in that: the n-value bit weight quantizer has bit weight lines W0, W1, W2, ...Wn-1, and the n-value amplitude weight quantizer has bit weight lines F0, F1, F2, ...Fn-1; the 0-bit weight line W0 of the n-value bit weight quantizer is directly connected with the 0-bit weight line F0 of the n-value amplitude weight quantizer; the other bit weight lines are connected in a manner of being reversely connected according to serial numbers: W1 is connected with Fn-1, W2 is connected with Fn-2, W3 is connected with Fn-3, ...and Wn-1 is connected with F1; an amplitude weight input end of the n-value amplitude weight quantizer serves as an input end of the variable compensation device; and an amplitude weight output end of the n-value amplitude weight quantizer serves as an output end of the variable compensation device.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to the realization of one of the basic hardware of multi-valued computer "quantization logic multi-valued amplitude weight changer" technical background [0002] So far all computers and their related digital systems are binary. Although multi-valued computing has many advantages, it develops very slowly because there is no key hardware supporting multi-valued computing. It can be said that multi-valued computers, especially decimal The realization of the computer is almost zero. In view of this situation, I have proposed a simple and effective multi-valued calculation implementation circuit, especially an effective method for ten-valued calculations and the addition and subtraction of multi-valued, especially ten-valued, implementations with binary hardware. , multiplication, and division arithmetic operations and key circuits of logic operations, which are called "quanti...

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Problems solved by technology

[0002] So far all computers and their related digital systems are binary. Although multi-valued computing has many advantages, it develops very slowly because there is no key hardware supporting multi-valued computing. It can be said that multi-valued computers, especially decimal The realization of the computer is almost zero. In view of this situation, I have proposed a simple and effective multi-valued calculation implementation circuit, especially an effective method for ten-valued calculations and the addition and subtraction of multi-valued, especially ten-valued, implementations with binary hardware. , multiplication, and division arithmetic operations and key circuits of logic operations, which are called "quantization logic" and its circuits. For details, refer to the patent application (201710023530.1201710023529.9201710023528.4201710024248.5201710024246.6201710024247.0). The quantization logic itself has two information modes, one One is the bit weight information mode, and the other is the width weight information mode. The specific circuits in the two information modes are also quite different. In actual work, the bit weight information and the width weight information are converted to each other. The numerical operation of value information depends on bit weight information, but the performance of natural information is mostly analog information, so obtaining standard bit weight and amplitude weight information will be the key to the actual application of the circuit, and the multi-valued storage method of amplitude weight information is also what we expected

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