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A synchronous self-calibration method for multi-channel high-speed data reception

A high-speed data and data synchronization technology, applied in the field of signal processing, can solve the problems of complex debugging process, unfavorable product application of data acquisition system, and not widely used, and achieve the effect of ensuring accuracy

Active Publication Date: 2021-07-30
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The latter is not widely used due to the complex commissioning process and the need for additional high-precision time interval measurement devices
Although the former is simple to debug and easy to stabilize, there is no automatic synchronization correction method at present, which is very unfavorable for the actual product application of this type of data acquisition system

Method used

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  • A synchronous self-calibration method for multi-channel high-speed data reception
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  • A synchronous self-calibration method for multi-channel high-speed data reception

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Embodiment

[0035] Figure 4 It is a functional block diagram of automatic correction of multi-channel high-speed data reception synchronization in the present invention.

[0036] In this example, if Figure 4 As shown, a kind of synchronous self-calibration method of multi-channel high-speed data reception of the present invention comprises the following steps:

[0037] S1. Configure the high-speed multi-core ADC chip into a test mode. In the test mode, each core of the ADC outputs a data synchronization clock signal with the same frequency and a sawtooth serial data signal that changes sequentially from 0-255, and then Input multiple data synchronous clock signals and sawtooth serial data signals to FPGA;

[0038] In this embodiment, taking EV8AQ165 as an example, the ADC chip is composed of four sub-cores with a sampling rate of 1.25GSPS, and outputs four 8-bit serial data streams DATA_A, DATA_B, DATA_C, DATA_D and four channels of data synchronization with the same frequency Clocks...

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Abstract

The invention discloses a synchronous self-calibration method for multi-channel high-speed data reception, using multi-core ADC to generate data and clock signals in test mode, and then setting the optimal delay value, using serial-to-parallel conversion module, multi-channel data real-time Comparing the module and the delay controller, the multi-channel high-speed data flow of the multi-core ADC is slowed down to receive, so as to complete the automatic correction of the delay of the BUFR reset signal, so as to ensure the correct reception and storage of the multi-channel high-speed data of the multi-core ADC, so as to realize the effective high-speed data Flatten.

Description

technical field [0001] The invention belongs to the technical field of signal processing, and more specifically relates to a synchronous self-calibration method for multi-channel high-speed data reception. Background technique [0002] With the rapid development of science and technology, the frequency and complexity of electrical signals have increased sharply, and the requirements for the sampling rate of the acquisition system have increased accordingly. At present, the more popular method is to use time-alternating parallel sampling technology (TIADC) to increase the sampling rate of the acquisition system. However, it is restricted by the sampling rate of the current single ADC chip, and the current mainstream method is to use an advanced high-sampling rate ADC chip. Most high-sampling-rate ADC chips are based on multi-core multi-channel high-speed data parallel output, while the data receiving processor (usually a field programmable gate array, FPGA) can only receive e...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/42
CPCG06F13/4291G06F13/4295
Inventor 黄武煌孙凯陈天添赵勇邱渡裕谭峰郭连平曾浩叶芃
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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