Semiconductor device and manufacturing method thereof
A manufacturing method and semiconductor technology, applied in the direction of semiconductor devices, electrical solid devices, electrical components, etc., can solve the problems of reducing production efficiency and increasing manufacturing costs, and achieve the effects of improving production efficiency, reducing manufacturing processes, and making manufacturing processes faster
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Embodiment 1
[0030] Please refer to figure 2 with image 3 , present embodiment 1 provides a kind of manufacturing method of the semiconductor device that can reduce manufacturing cost and improve production efficiency, and present embodiment is described taking single-chip microcomputer (MCU) as example, and its specific steps include:
[0031] Step 101, providing a substrate 10;
[0032] Step 102, respectively forming a split-gate flash memory device unit 20 and a logic device unit 30 on the substrate 10; wherein the split-gate flash memory device unit 20 is the memory part of the single-chip microcomputer, and wherein the logic device unit 30 is the logic of the single-chip microcomputer Control section.
[0033] Step 103, using the NPLUS mask and phosphorous ions to perform an ion implantation process on the split-gate flash memory device unit 20 and the logic device unit 30 simultaneously, thereby forming an N-type drain region (N-type drain region) in the split-gate flash memory d...
Embodiment 2
[0036] Please refer to Figure 4 to Figure 8 , the manufacturing method of the semiconductor device provided in the second embodiment, the specific steps are as follows:
[0037] Step 201, providing a substrate 10, such as Figure 5 shown.
[0038] Step 202, respectively forming the split-gate flash memory device unit 20 and the logic device unit 30 on the substrate 10, such as Figure 5 shown. Wherein, the split-gate flash memory device unit 20 is the memory part of the single-chip microcomputer, and the logic device unit 30 is the logic control part of the single-chip microcomputer.
[0039] Please refer to Figure 5 The step of forming the split-gate flash memory device unit 20 in this step 202 includes: forming a tunnel oxide layer 21, a floating gate 22, a word line 23, sidewalls 24, a source region 25 and a source electrode on the substrate 10 line 26 , and a bit line 27 extending upward along the substrate 10 and spaced from the spacer 24 . The steps of forming th...
Embodiment 3
[0050] Please refer to Image 6 , the third embodiment provides a semiconductor device, including a split-gate flash memory device unit 20 and a logic device unit 30 formed on the same substrate 10 .
[0051] Wherein, the split-gate flash memory device unit 20 includes a tunnel oxide layer 21, a floating gate 22, a word line 23, a sidewall 24, a source region 25, and a source line 26 formed on the substrate 10, and along the The bit line 27 extending upward from the substrate 10 and spaced from the sidewall 24, the outer side of the sidewall 24 of the split-gate flash memory device unit 20 is formed with a first spacer oxide layer 29, the first spacer There is a gap between the oxide layer 29 and the bit line 27 , and a heavily doped N-type drain region 28 is formed in the substrate 10 between the first interval oxide layer 29 and the bit line 27 .
[0052] Wherein, the logic device unit 30 includes an insulating oxide layer 31 and a gate structure 32 formed on the substrate ...
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