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3D integrated circuit device having a buttress structure for resisting deformation

A technology of integrated circuits and wall structures, applied in the field of high-density integrated circuit devices

Inactive Publication Date: 2018-12-07
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These positional changes can cause alignment issues with the upper layer structures and often in back-end-of-line (BEOL) routing cause misconnections with the patterned conductor layers implemented above the stack and / or misalignment

Method used

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  • 3D integrated circuit device having a buttress structure for resisting deformation
  • 3D integrated circuit device having a buttress structure for resisting deformation
  • 3D integrated circuit device having a buttress structure for resisting deformation

Examples

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Embodiment Construction

[0073] refer to Figure 3 to Figure 1 0 to provide a detailed description of embodiments of the present invention.

[0074] image 3 is a heuristic layout illustrating an integrated circuit device that includes a stack region 310 above a substrate and a region 320 outside the stack region 310 . The stack includes a plurality of layers disposed in the stack region 310 . A plurality of circuit elements 371 extend through the stack. Electrical conductors (not shown) in the patterned conductor layer above the stack are connected to one or more of the circuit elements 371 . The lamination region 310 may include a plurality of laminations. The stack includes active layers, such as conductors involved in circuit function, and passive layers, such as insulators that first operate to electrically isolate the active layers in the stack.

[0075] In this example, stair step structures are disposed in regions 301 , 302 , 303 , 304 and may be configured as wordline landing pads, for e...

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PUM

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Abstract

An integrated circuit includes a stack in a stack region and a region outside the stack region. A buttress structure disposed outside the stack includes a fence-shaped, electrically passive element configured to oppose expansion of materials outside the stack region in a direction toward the stack region.

Description

technical field [0001] The present invention relates to high density integrated circuit devices, including three-dimensional (3D) memory devices, that can be subjected to deformation stress during fabrication. Background technique [0002] A three-dimensional integrated circuit includes a stack of materials in which multiple planes of circuit elements are arranged. For example, techniques have been developed for stacking multiple levels of memory cells to achieve higher storage capacities. Researchers have developed various structures such as Bit Cost Scalable (BiCS) memory, Terabit Cell Array Transistor (TCAT), and Vertical NAND (V-NAND) . For these types of structures, and other complex structures that include stacks of active layers separated by insulating (or passive) layers, conductors or other circuit elements are formed to connect layers deeper in the stack to upper layers It is often useful to connect layers deep in the stack to patterned metal layers that are loc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11556H01L27/11582
CPCH10B41/27H10B43/27H01L23/562H01L23/585H10B43/50H10B43/40
Inventor 骆统洪永泰杨大弘陈光钊
Owner MACRONIX INT CO LTD