Increased refresh interval and energy efficiency in DRAM

Abstract

The techniques described herein generally include a method and system related to the design and operation of DRAM devices with significantly reduced refresh energy usage. A method for designing a DRAMoptimizes or otherwise improves the DRAM for energy efficiency based on a measured or predicted probability of failure of a memory cell in the DRAM. DRAM may be configure to operate at an increased post-refresh interval, which reduces DRAM refresh energy, but causes a predictable portion of memory cells in DRAM to leak power too quickly to hold data. The DRAM is further configured by a selected number of spare memory cells to replace the leaking memory cells so that the DRAM can operate at an increased post-refresh interval with minimal or no reduction in DRAM capacity.

Description

[0001] This application is a divisional application of a Chinese application with a filing date of September 1, 2013, an application number of 201380079300.7 (PCT / US2013 / 057757), and an invention title of "Increased Refresh Interval and Energy Efficiency in DRAM". technical field [0002] The present disclosure relates to increased refresh intervals and energy efficiency in dynamic random access memory (DRAM). Background technique [0003] Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section. [0004] There is a trend towards large-scale chip multiprocessors comprising a relatively large number of processor cores, with core counts expected to be in the hundreds or thousands in the near future. For applications with high levels of parallelism, such as applications in which multiple computations are performed simultaneously or in parallel ...

AI Technical Summary

Problems solved by technology

This situation leads to a phenomenon known as a "power wall," "utility wall," or "dark silicon," where an increasing portion of a high-core-count chip's multiprocessor cannot be powered at full frequency or at all.

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