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SRAM read multiplexer including replica transistors

A technology of transistors and selection transistors, used in instruments, static memory, digital memory information, etc., to solve problems such as errors

Active Publication Date: 2019-02-05
STMICROELECTRONICS SRL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This causes an error when bitlines BL0 and BLB0 are read

Method used

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  • SRAM read multiplexer including replica transistors
  • SRAM read multiplexer including replica transistors
  • SRAM read multiplexer including replica transistors

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Embodiment Construction

[0019] The drawings and the following description relate to the preferred embodiment by way of illustration only. It should be noted that, from the discussion below, alternative embodiments of the structures and methods disclosed herein will be readily identified as viable alternatives that may be employed without departing from the principles of the embodiments.

[0020] Reference will now be made in detail to several embodiments, examples of which are illustrated in the accompanying drawings. It should be noted that, where practicable, similar or similar reference numerals may be used in the figures and may indicate similar or similar functionality. The figures show embodiments for illustrative purposes only. As described herein, a "replicated" transistor has the same length and width, or substantially similar or substantially the same electrical properties as the transistor it is replicated from.

[0021] now refer to Figure 2A The SRAM memory circuit 100 is described. ...

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Abstract

The invention relates to SRAM read multiplexer including replica transistors. A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to abit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a secondconduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.

Description

technical field [0001] This application relates to the field of static random access memory (SRAM) circuits, and more particularly to SRAM circuits that utilize replica transistors to compensate for current injected into a bit line through parasitic capacitance. Background technique [0002] now refer to Figure 1A A prior art SRAM memory circuit 50 is described. SRAM memory circuit 50 includes first and second columns 52 and 54 . A first column 52 includes memory cells 51 having a bit line BL0 and a complementary bit line BLB0 associated therewith. A second column 54 includes memory cells 53 having a bit line BL1 and a complementary bit line BLB1 associated therewith. Column selection circuit 60 includes a PMOS transistor M1 whose source is coupled to complementary bit line BLB0, whose drain is coupled to node INN, and whose gate is biased by control signal CTRL1. PMOS transistor M2 has its source coupled to bit line BL0, its drain coupled to node INP, and its gate biase...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/419
CPCG11C11/419G11C5/14G11C7/227G11C2207/002G11C11/417
Inventor K·J·多里A·帕沙克S·库马尔
Owner STMICROELECTRONICS SRL