Ladder structure for double-sided wiring of three-dimensional memory devices
A technology of three-dimensional storage and ladder structure, which is applied in semiconductor devices, electric solid-state devices, semiconductor/solid-state device components, etc., and can solve the problem of high cost
Active Publication Date: 2019-11-22
YANGTZE MEMORY TECH CO LTD
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- Claims
- Application Information
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Problems solved by technology
However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly
As a result, the storage density of planar memory cells approaches the upper limit
Method used
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[0016] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure can also be used in a variety of other applications.
[0017] It is noted that references in the specification to "one embodiment," "an embodiment," "exemplary embodiment," "some embodiments," etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but Not every embodiment may include that particular feature, structure or characteristic. Furthermore, such phrases are not necessarily referring to the same embodiment. In addition, when a particular feature, structure or characteristic is described in connection with an embodim...
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Embodiments of a ladder structure for double-sided wiring of a three-dimensional (3D) memory device are disclosed. In an example, a 3D memory device includes a substrate, a memory stack layer disposed over the substrate and including alternately stacked conductor / dielectric layer pairs, and an array of memory strings, each memory string extending vertically through the memory stack layer inner area. The outer area of the memory stack layer includes a first stepped structure disposed on the substrate and a second stepped structure disposed above the first stepped structure. In the first ladder structure, the first edges of the conductor / dielectric layer pairs along the vertical direction away from the substrate are laterally staggered away from the array of memory strings. The second edges of the conductor / dielectric layer pairs along the vertical direction away from the substrate in the second ladder structure are laterally staggered toward the array of memory strings.
Description
Background technique [0001] Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods of manufacturing the same. [0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. As a result, the storage density of planar memory cells approaches the upper limit. [0003] 3D memory architectures can address density limitations in planar memory cells. A 3D memory architecture includes a memory array and peripherals for controlling signals to and from the memory array. Contents of the invention [0004] Embodiments of a ladder structure for double-sided wiring of a 3D memory device are disclosed herein. [0005] In one example, a 3D memory device includes a substrate, a memory stack layer disposed ...
Claims
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IPC IPC(8): H01L27/1157H01L27/11578H10B43/27H10B43/35H10B43/10H10B43/20
CPCH10B43/20H10B43/35H10B43/10H10B43/50H10B43/27H01L23/5226H01L23/528
Inventor S-F·S·鞠
Owner YANGTZE MEMORY TECH CO LTD