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A method to obtain the whole picture of power MOS layout design

A layout design, full-view technology, applied in computer-aided design, computing, instrumentation, etc., can solve problems such as long analysis iteration cycle, unpredictable reliability and performance of PowerIC products, and inability to meet

Active Publication Date: 2020-04-07
北京华大九天科技股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Traditional RC extraction schemes cannot meet the needs of Power IC designers to understand the full picture of Power ICs
The Power IC module has the characteristics of special shape, large area, design conforming to DRC / LVS rules but still fails, accurate voltage and current simulation is difficult to complete with traditional RC extraction and emulator, and analysis iteration cycle is long, etc., resulting in unguaranteed accuracy and speed. In the case of solutions, Power IC design cannot predict the reliability and performance of Power IC products, and design risks and product development cycle risks coexist

Method used

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  • A method to obtain the whole picture of power MOS layout design
  • A method to obtain the whole picture of power MOS layout design
  • A method to obtain the whole picture of power MOS layout design

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Embodiment Construction

[0022] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described here are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0023] figure 1 For the flow chart of the method for obtaining the overall picture of the Power MOS layout design according to the present invention, reference will be made below figure 1 , The method for obtaining the overall picture of Power MOS layout design of the present invention is described in detail.

[0024] First, in step 101, the M1 resistance outside the coverage area of ​​the source and drain terminals is extracted without dividing the Power MOS transistor.

[0025] figure 2 It is a schematic diagram of the Power MOS undivided according to the embodiment of the present invention, such as figure 2 As shown, the MOS tube is not divided, and the source and drain ends...

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Abstract

A method for obtaining a panorama of a power MOS layout designcomprise the following steps: 1) extracting the M1 resistor outside the source end and the drain end coverage area without dividing the pow MOS transistor; 2) slicing that power MOS transistor and extract parameter information; 3) extracting topology information of specific parameters in Power MOS layout design; 4) inputting topologicalinformation of parameters into SPICE for simulation. The invention can obtain I-V characteristics (voltage and current characteristics) of the entire Power MOS layout design, namely obtaining the characteristic panorama of the entire Power MOS layout design, which provides a basis for reliability analysis of Power IC.

Description

Technical field [0001] The present invention relates to the field of layout design in EDA tools, and particularly relates to a method for obtaining a complete picture of Power MOS layout design. By dividing a large-scale power MOS tube (Power MOS), all metals distributed in the Power MOS layout are extracted. Compared with traditional extraction methods, via, contact and diffusion can better reflect the overall picture of Power MOS layout design. Background technique [0002] How to simulate the real working status of Power IC products and improve the reliability and yield of Power IC products is a problem that Power IC designers always face. Traditional RC extraction solutions cannot meet the needs of Power IC designers to understand the full picture of Power IC. The Power IC module has the characteristics of special shape, large area, design conforming to DRC / LVS rules but still invalid, accurate voltage and current simulation is difficult to complete with traditional RC extra...

Claims

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Application Information

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IPC IPC(8): G06F30/392
CPCG06F30/392
Inventor 李雷魏洪川陆涛涛
Owner 北京华大九天科技股份有限公司
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