Method, device, readable storage medium and system for improving response speed of ncq command

Abstract

The invention discloses a method for improving the response speed of an NCQ command, which includes: confirming the current application states of the first FIFO and the second FIFO when a computer command is detected; The target FIFO transmits the detected computer commands. The invention also discloses a device, a readable storage medium and a system for improving the response speed of the NCQ command. The invention realizes the transmission of communication commands by increasing the number of FIFOs, avoids the waiting time of command transmission and improves the beneficial effect of NCQ command transmission efficiency.

Description

technical field [0001] The present invention relates to the technical field of NCQ command response, in particular to a method, device, readable storage medium and system for improving the response speed of NCQ command. Background technique [0002] At present, in the SATA (Serial Advanced Technology Attachment serial ATA interface specification) controller equipment (mainly including solid-state drives) on the market, the SATA controller (Serial Advanced Technology Attachment serial ATA interface specification controller) has a FIFO (First input firstoutput, buffer, support first-in-first-out principle) to receive data from Host (computer) or Device (terminal device). The current processing strategy is to receive the next NCQ ( NativeCommand Queuing, native command queue) command, in order to ensure that the data passed to the Device does not have CRC (Serial Advanced Technology Attachment, Serial ATA interface specification, before starting the sending and receiving of the...

AI Technical Summary

Problems solved by technology

This has resulted in two problems: one, reducing the response rate of SATA; two, for those NCQ1 applications that deal with non-alignment, it will increase its processing complexity, because FTL (Faster-Than-Light, FTL or Called Superluminal) for non-aligned commands, it is necessary to judge whether the next command can be continued before receiving the tail data, which is in conflict with the SATA controller not accepting the next command without clearing the FIFO data

However, in the current design, the data in the FIFO must be transmitted to the Device Ram to transmit the next command, which reduces the response rate of the command, and the overall effective bandwidth of sata is also reduced, and the response delay and speed requirements are relatively high. This is a design flaw for users of

Images