Intelligent Defect Correction System and Implementation Method

Abstract

The present invention provides an intelligent semiconductor defect correction system and its implementation method. The method includes: receiving a plurality of defect data sent by a manufacturing factory, receiving IC design layout data from an integrated circuit design company, and analyzing the plurality of defect data After the defect coordinate conversion correction and defect image correction, the key area analysis is used to analyze the corrected defect data and design layout graphics to improve the accuracy of key area analysis and accurately determine the open circuit or short circuit failure caused by each defect image Fatal defect index; then according to the fatal defect index and defect signal parameters, fatal defects are distinguished into high-risk defects, medium-risk defects and low-risk defects, etc., to achieve an improved intelligent defect correction system and its implementation method accuracy and precise identification of fatal defects Purpose.

Description

Technical field [0001] The present invention relates to a smart type semiconductor defect correction, classification, and sampling system and its implementation method;,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Manufacturing factories, mask manufacturing plants, LED manufacturing, or assemblers intelligent defect correction, classification and sampling system and their implementation methods. Background technique [0002] In general, in the factory, manufacturing the integrated circuit (Integrated Circuit; IC) is formed by mask, semiconductor microside, etching, film deposition, copper process, chemical mechanical polishing and multiple exposure, and processes. . Therefore, throughout the manufacturing process, it is possible to generate random defects and systemic defects due to the accuracy deviation of the equipment itself, abnormal failure, particle generated particles, design layout drawings and yellow light process window (WINDOW). Random and systematic defects,...

AI Technical Summary

Problems solved by technology

Therefore, during the entire manufacturing process, random defects and systematic defects may occur due to the accuracy deviation of the equipment itself, abnormal faults, particles generated during the process, drawing defects in the design layout, and insufficient yellow light process windows (window) Random and systematic defect), these defects cause product open circuit (open) or short circuit (short) type failure, reduce wafer yield

These random defects and systematic defects, as the size of the semiconductor manufacturing process shrinks down, the number of defects also increases greatly due to the reduction in size, so that thousands or tens of thousands of defects can be obtained in each defect detection, due to the limitation of the scanning electron microscope (Scanning Electron Microscope, SEM) can only select dozens to hundreds of defects to take pictures by sampling, which greatly increases the difficulty of sampling defects that will actually cause open circuit or short circuit failure, so it cannot be accurate and real-time Provide SEM photos of defects that cause yield loss to process engineers, and it is difficult to analyze the source of defects in the process based on the SEM photos of defects. Therefore, the effect of improving defect yield is not good, and the cost of semiconductor factories is increased.

[0003] In the practical operation of semiconductor factories (for example: wafer foundry, Foundry), the data analysis of real-time (real-time) defects and image graphics classification was an important method to improve yield in the past, but this method is in the nanometer It is difficult to find fatal defects in the defect analysis of high-level semiconductor manufacturing process; the core part of this innovation introduces IC design layout data, critical area analysis (Critical Area Analysis, CAA) method, defect pattern overlapping design layout, coordinate conversion Correction system and defect size correction system are important breakthrough methods and systems to solve fatal sampling defects

[0004] Furthermore, the image profile measurement data of the SEM and optical microscope and the defect data generated by the inspection machine are compared with the key area analysis data, and the defect size and area data of the inspection machine and the image profile of the SEM and optical microscope are compared. There are differences in the measurement size and area data, resulting in differences in the analysis results of key areas. In order to solve the analysis deviation of key areas, the problem of defect size deviation must be solved

For example: the defect size measurement unit of the defect inspection machine should be higher than the minimum size of the layout graphics, resulting in a deviation between the size of the defect data and the actual defect size of the SEM photo

[0005] In addition, in the complex advanced process of miniaturized semiconductors, especially when the optical effect process window (process window) is getting narrower and narrower, but the IC design layout pattern is multiplied and complicated, resulting in some pattern-related defects being detected Out of them, the defects that will affect the yield rate are "systematic defects", which will cause extremely low yield rate, but if this graphic does not affect the IC design circuit, such as: monitoring graphics, because it does not affect the yield rate, that is It belongs to "false defect", but because the false defect pattern and signal are obvious, it often accounts for most of the defect sampling ratio to more than 90%, but it is impossible to really find the defect pattern of open circuit or short circuit failure

[0006] Finally, in the defect sampling part, in addition to the patent number US8312401B2 approved by the same inventor in 2012, the critical area analysis method was used to obtain the key area of ​​the design layout pattern within the defect size and coordinate deviation range of each defect, and calculated The probability value of open circuit or short-circuit failure defects is the Killer Defect Index (KDI), which is the CAA value; however, when calculating the Killer Defect Index (KDI), the defect inspection machine is not loaded with the wafer The precision of the control motor is taken into account, for example: when the defect inspection machine moves the wafer, the coordinate accuracy unit is controlled as plus or minus W, for example, when W is equal to 0.05 microns, therefore, the size it can detect is plus or minus 0.05 microns multiples; therefore, it may cause the size value of the detected defect image to be larger than the actual size, which may cause problems such as a high fatal defect index

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