Synchronization Detection Method of Acquisition Channels in Digital Integrated Circuit Test System

Abstract

The invention discloses a method for detecting the synchronization of acquisition channels in a digital integrated circuit test system. According to needs, one channel is selected as a reference channel, and the rest are used as channels to be detected, and the frequency of the working clock of the digital integrated circuit test system is reduced as a calibration signal. The calibration signal is delayed and sent to the reference channel and the channel to be detected, and the delay is increased according to the preset adjustment step, and the frequency of the working clock is multiplied as the sampling clock, and the acquisition signal of the reference channel and the nth channel to be detected Sampling is performed, and judgment is made according to the sampling signals obtained by the reference channel and the channel to be detected during the delay increase process, so as to determine the delay of the channel to be detected relative to the reference channel. The invention can detect the channel delay less than the sampling period, and the measurement accuracy is determined by the delay accuracy, which can greatly reduce the requirement on the frequency of the sampling clock and reduce the implementation complexity of the whole method.

Description

technical field [0001] The invention belongs to the technical field of digital integrated circuit test systems, and more specifically relates to a method for detecting synchronization of acquisition channels in a digital integrated circuit test system. Background technique [0002] With the continuous advancement of science and technology, the speed of integrated circuits continues to accelerate, the performance is more and more complex, and the number of pins is increasing. These highly integrated circuits are only connected to external circuits through limited pins, which brings many difficulties to how to judge the quality of integrated circuits, and puts forward higher requirements for integrated circuit testing equipment for testing integrated circuit functions and performance. [0003] With the acceleration of digital integrated circuit operation speed and the gradual increase of external pins, the output signal rate of digital integrated circuit test system has reache...

AI Technical Summary

Problems solved by technology

However, this method will be limited by the sampling frequency. According to the sampling theorem, if the delay error Δt between two channels is to be collected, the sampling clock frequency f must satisfy: f≥2 / Δt

For example: when Δt=100ps, f≥20GHz, it is very difficult to realize in practice, and the cost will increase greatly

Images