Method for detecting synchronization of acquisition channel in digital integrated circuit test system

Abstract

The invention discloses a method for detecting synchronization of an acquisition channel in a digital integrated circuit test system. One channel is selected as a reference channel according to requirements, and the rest of channels serve as channels to be detected, a working clock of a digital integrated circuit test system is subjected to frequency reduction to serve as a calibration signal, thecalibration signal is delayed and then sent to the reference channel and the channels to be detected, delay is increased according to the preset adjustment step length, the working clock is subjectedto frequency doubling to serve as a sampling clock, acquisition signals of the reference channel and the nth channel to be detected are sampled, judgment is performed according to the acquisition signals obtained by the reference channel and the channels to be detected in the delay increase process, and therefore the delay of the channels to be detected relative to the reference channel is determined. By means of the method, the channel delay less than the sampling period can be detected, the measurement precision is determined by the delay precision, the requirement for the sampling clock frequency can be greatly reduced, and the implementation complexity of the whole method is reduced.

Description

technical field [0001] The invention belongs to the technical field of digital integrated circuit test systems, and more specifically relates to a method for detecting synchronization of acquisition channels in a digital integrated circuit test system. Background technique [0002] With the continuous advancement of science and technology, the speed of integrated circuits continues to accelerate, the performance is more and more complex, and the number of pins is increasing. These highly integrated circuits are only connected to external circuits through limited pins, which brings many difficulties to how to judge the quality of integrated circuits, and puts forward higher requirements for integrated circuit testing equipment for testing integrated circuit functions and performance. [0003] With the acceleration of digital integrated circuit operation speed and the gradual increase of external pins, the output signal rate of digital integrated circuit test system has reache...

AI Technical Summary

Problems solved by technology

However, this method will be limited by the sampling frequency. According to the sampling theorem, if the delay error Δt between two channels is to be collected, the sampling clock frequency f must satisfy: f≥2 / Δt

For example: when Δt=100ps, f≥20GHz, it is very difficult to realize in practice, and the cost will increase greatly

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