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Method and apparatus for writing nonvolatile memory using multiple-page programming

A technology of flash memory and programming voltage, applied in static memory, read-only memory, information storage, etc., which can solve the problems of low programming speed and/or clearing speed

Inactive Publication Date: 2019-07-23
许 富菖
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For some applications, the low programming speed and / or erasing speed in non-volatile memory storage becomes a limitation and / or disadvantage

Method used

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  • Method and apparatus for writing nonvolatile memory using multiple-page programming
  • Method and apparatus for writing nonvolatile memory using multiple-page programming
  • Method and apparatus for writing nonvolatile memory using multiple-page programming

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Embodiment Construction

[0032] Exemplary embodiments of the present invention are described below in the context of a method, apparatus, and apparatus for writing to non-volatile flash memory using multi-page programming.

[0033] Those of ordinary skill in the art will understand that the following detailed description of the present invention is exemplary only and is not intended to be limiting in any way. Other embodiments of the present invention will readily suggest themselves to those skilled in the art having the benefit of this disclosure. Reference will now be made in detail to the description to implement the exemplary embodiments of the invention as in the accompanying drawings. The same reference numbers (or reference numerals) will be used throughout the drawings and the following detailed description to refer to the same or like parts.

[0034] The components, process steps, and / or structures described herein may be implemented using different types of operating systems, computing plat...

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Abstract

Methods and apparatus for writing to a non-volatile 3D NAND flash memory using multi-page programming. A method for multiple-page programming of an array is provided. The array has a block including aplurality of page groups, and each page group includes a plurality of cell strings forming a plurality of pages. The method includes deactivating a drain select gate (DSG) and a source select gate (SSG), applying a programming voltage to a selected word line, and applying a medium-high voltage to a non-selected word line. The method also includes repeating the plurality of programming operationswhile maintaining the word line voltage level from the first programming operation to the last programming operation. Wherein each programming operation comprises the steps of loading data on a bit line; and pulsing a drain select gate associated with the selected page group to load data into the selected page in the selected page group.

Description

[0001] priority [0002] This application is a continuation-in-part of US Patent Application No. 14 / 846,673, filed on September 4, 2015, entitled "Method and Apparatus for Writing to Non-Volatile Memory Using Multi-Page Programming" (CIP ). Application 14 / 846,673 claims the benefit of priority based on U.S. Provisional Patent Application Serial No. 62 / 046,902, filed September 6, 2014, entitled "NAND Flash Memory Using Multi-Page Programming," the entire contents of which are Incorporated herein by reference. [0003] This application claims the benefit of priority based on U.S. Provisional Patent Application Serial No. 62 / 617,220, filed January 13, 2018, entitled "3D NAND Flash Memory Using Multi-Page Programming," the entire contents of which are via Reference is incorporated in this application. [0004] This application claims the benefit of priority based on US Provisional Patent Application Serial No. 62 / 628,275, filed February 8, 2018, entitled "3D NAND / DRAM Array Using...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/10G11C16/04G11C16/08
CPCG11C16/10G11C16/0483G11C16/08
Inventor 许富菖
Owner 许 富菖