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Array substrate and testing method thereof

A technology of array substrate and test terminal, which is applied in the direction of instruments, semiconductor devices, electrical components, etc., can solve the problem of high production cost of test equipment, and achieve the effect of low production cost and small size

Active Publication Date: 2021-12-10
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The invention provides an array substrate and a testing method thereof, which can solve the problem of high production cost of testing equipment in the related art

Method used

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  • Array substrate and testing method thereof
  • Array substrate and testing method thereof
  • Array substrate and testing method thereof

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Embodiment Construction

[0050] In order to make the purpose, technical solution and advantages of the present invention clearer, the following will further describe in detail the embodiments of the present invention in conjunction with the accompanying drawings.

[0051]The transistors used in all the embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics, and the transistors used in the embodiments of the present invention are mainly switching transistors according to their functions in circuits. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiments of the present invention, the source is called the first pole, and the drain is called the second pole. According to the form in the accompanying drawings, it is stipulated that the middle terminal of the transistor is the gate, the signal input terminal is the source terminal, and ...

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Abstract

The invention discloses an array substrate and a testing method thereof. The array substrate includes a plurality of clock signal lines and a plurality of test terminals. Since at least two of the multiple clock signal lines can be connected to the same test terminal, compared to the connection of one clock signal line to one test terminal in the related art, the required settings on the array substrate provided by the embodiment of the present invention Correspondingly, the number of pins required to be included in the test equipment connected to the test terminals on the array substrate provided by the embodiment of the present invention can be less, the production cost of the test equipment is lower, and the volume is smaller. Small.

Description

technical field [0001] The invention relates to the field of display technology, in particular to an array substrate and a testing method thereof. Background technique [0002] Currently, a gate driver on array (GOA) technology can be used to integrate a gate driver circuit on an array substrate. The gate driving circuit can be connected with multiple clock signal lines and the pixel unit, and the gate driving circuit can control the operation of the pixel unit according to the clock signal provided by the clock signal line. [0003] In the related art, in order to ensure the product yield, the performance test of the gate driving circuit may be performed before leaving the factory, for example, an array test (array test, AT). When testing, multiple test terminals can be set on the array substrate, and each test terminal can be respectively connected to a clock signal line and a pin of the test equipment, and the test equipment can provide each clock signal line through eac...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G09G3/00
CPCG09G3/006G09G2300/0426G09G2310/0286G09G3/3233H01L27/124H01L27/0292H01L27/0251H01L27/1255
Inventor 袁志东李永谦袁粲
Owner BOE TECH GRP CO LTD