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An adaptive dram refresh control method and a dram refresh controller

A control method and adaptive technology, applied in the field of memory, can solve problems such as system performance loss, and achieve the effects of reducing system performance loss, reducing transient refresh power consumption, and improving read and write access efficiency

Active Publication Date: 2021-10-26
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, after the read / write operation is back-pressured (that is, the read / write operation is stopped), precharge (precharge) and reactivation (activation) are required, which will cause system performance loss

Method used

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  • An adaptive dram refresh control method and a dram refresh controller
  • An adaptive dram refresh control method and a dram refresh controller
  • An adaptive dram refresh control method and a dram refresh controller

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Embodiment Construction

[0040] The present invention will be further described below in conjunction with accompanying drawing.

[0041] The self-adaptive DRAM refresh controller provided by the present invention is based on the existing DRAM refresh controller, and a cache area is set between the tREFI counter and the command controller to cache refresh instructions. When the read / write is in progress, the refresh instruction will be cached, so as to ensure that the read / write will not be interrupted and affect the efficiency. When the bus is idle, the cache refresh instruction will be sent to the DRAM.

[0042] figure 2 Shown is the first implementation of the present invention, specifically on the basis of the existing DRAM refresh controller, a FIFO is set between the tREFI counter and the command controller to refresh the instruction cache, and the upper limit value of the FIFO cache is set to Y , the value of Y is determined according to the number of refreshes allowed to be postponed by the D...

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PUM

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Abstract

In order to reduce the system performance loss caused by the existing DRAM refresh controller sending refresh instructions based on tREFI, the present invention provides an adaptive DRAM refresh control method and a DRAM refresh controller. The present invention caches the refresh instructions first, and then judges the state of the read-write bus. If the read-write bus is idle, the cached refresh instructions are sequentially sent to the DRAM; The refresh commands are sent to DRAM in sequence.

Description

technical field [0001] The invention belongs to the technical field of memory, and relates to an adaptive DRAM refresh control method and a DRAM refresh controller. Background technique [0002] Such as figure 1 As shown in the figure (a), the traditional DRAM refresh controller sends refresh commands based on tREFI (average refresh interval, DRAM JEDEC terminology). When the tREFI counter reaches the count value (usually 7.8 microseconds), it first needs to back pressure the previous stage The normal read / write command generated by the circuit (that is, pressed so that the read / write command is not sent), and then send a refresh command to the DRAM. After the read / write operation is back-pressed (that is, the read / write operation is stopped), precharge (precharge) and reactivation (activation) are required, which will cause system performance loss. [0003] Such as figure 1 As shown in the figure (b), when the write transmission is interrupted by the refresh command, the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/406
CPCG11C11/406
Inventor 李乾男王帅王龙
Owner XI AN UNIIC SEMICON CO LTD