Data acquisition synchronization device and method based on FPGA TDC

Abstract

The invention discloses a data acquisition synchronization device and a data acquisition synchronization method based on FPGA TDC. The device comprises a sampling module (1) used for carrying out theanalog-to-digital conversion of an inputted analog waveform according to a sampling clock, and generating sampling point data; a receiving module (2) used for receiving sampling point data according to a working clock after the trigger signal arrives, and the working clock is generated by frequency division of the sampling clock; a delay chain (3) used for delaying the trigger signal; a latch module (4) used for latching the delayed trigger signal when the rising edge of the working clock arrives; an encoding module (5) used for calculating a time interval between the latched delayed trigger signal and the rising edge of the working clock; and a synchronization module (6) used for carrying out point shifting synchronization on the sampling point data according to the time interval. By measuring the time interval between the trigger signal and the rising edge of the triggered first working clock, the synchronization deviation of multiple acquisition board cards caused by the phase difference between the working clocks can be eliminated.

Description

technical field [0001] The present disclosure relates to the field of data processing, in particular, to an FPGA TDC-based data acquisition synchronization device and method. Background technique [0002] At present, the synchronization of multiple acquisition boards is mainly achieved by keeping the sampling clock frequency, phase and trigger consistent between different acquisition boards. To achieve this, one acquisition board can be used as the main board, and the main board can fan out clocks and triggers to other acquisition boards; or a dedicated clock and trigger board can be used to ensure that all acquisition boards are fully synchronized. Using the clock fan-out chip can generate multiple synchronous sampling clocks, which are provided to each acquisition board through basically consistent wiring or drivers. In addition, the trigger signal is also fanned out to all acquisition boards to ensure simultaneous acquisition. [0003] The analog-to-digital converter (An...

AI Technical Summary

Problems solved by technology

For multiple acquisition boards, the phase difference of the FPGA working clock leads to misalignment of sampling points in each data clock cycle. Even if each acquisition board receives the trigger signal at the same time, the sampling point data uploaded by each acquisition board will be deviation, which is unacceptable when reconstructing the waveform

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