A method and device for reading 3D NAND memory

Abstract

The invention provides a method and device for reading 3D NAND memory. Before the clock trigger signal, the reference bit line in each group is precharged to a preset voltage, and after address decoding, the target bit line and the reference bit line At the same time, by connecting the target bit line to the reference bit line, the target bit line is in a voltage readable state, and then, after the target word line is selected, the induced current on the target bit line is obtained. In this way, the precharge of the reference bit line does not need to occupy clock time, and the target bit line is in a readable voltage state through the connection with the reference bit line. Compared with the precharge method, this coupling method hardly takes up clock time and can greatly reduce The clock time of the read operation, meanwhile, can greatly reduce power consumption.

Description

technical field [0001] The invention relates to the field of integrated circuit design of memory, in particular to a method and device for reading 3D NAND memory. Background technique [0002] NAND flash memory is a non-volatile storage product with low power consumption, light weight and good performance, and has been widely used in electronic products. In order to further increase storage capacity and reduce storage cost per bit, 3D NAND memory has been proposed. [0003] In 3D NAND memory, memory cells form an array in three-dimensional directions, and when performing a read operation of memory cells, one way is to pre-charge all bit lines (BL, Bit Line) before the clock arrives. To the voltage Vdd, and when the word line (WL, Word Line) is triggered, these bit lines will be discharged, and the power consumption of this method is too large. Another way is to precharge the bit line of the target address to the voltage Vdd after the clock arrives and decode the address, th...

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Problems solved by technology

[0003] In 3D NAND memory, memory cells form an array in three-dimensional directions, and when performing a read operation of memory cells, one way is to pre-charge all bit lines (BL, Bit Line) before the clock arrives. To the voltage Vdd, and when the word line (WL, Word Line) is triggered, these bit lines will discharge, and the power consumption of this method is too large

Another way is to precharge the bit line of the target address to the voltage Vdd after the clock arrives and decode the address, then stop precharging, trigger the word line, and perform a read operation. In this way, the clock After the arrival, the bit line needs to be precharged, which will greatly increase the time consumption of the read operation and reduce the read efficiency

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