Structure and method for FinFET device with contact over dielectric gate

Abstract

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first fin active region and a second fin active region protruded from a semiconductor substrate; an isolation component formed in the semiconductor substrate and interposed between the first and second fin active regions; a dielectric gate disposed on the isolation component; a firstgate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source / drain component formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source / drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact component formed in a first inter-level dielectric material layer and landing on the first and second source / drain components and extending over the dielectric gate. Embodiments of the present invention relate to a structure and method for a FinFET device with a contact over a dielectric gate.

Description

technical field [0001] Embodiments of the present invention relate to FinFET device structures and methods with contacts over dielectric gates. Background technique [0002] Integrated circuits have advanced to advanced technologies with smaller feature sizes such as 16nm, 9nm and 7nm. In these advanced technologies, devices, such as transistors, shrink and thus cause various problems, such as contact-to-gate bridging problems. Furthermore, to enhance device performance, three-dimensional transistors with fin active regions are often required. Those three-dimensional field-effect transistors (FETs) formed on the active area of ​​a fin are also known as FinFETs. FinFETs are expected to have a narrow fin width for short channel control, which results in a smaller S / D region than that of a planar FET. This will further reduce the contact to S / D junction margin. As device dimensions shrink, contact dimensions continue to shrink for high density gate pitch requirements. In o...

AI Technical Summary

Problems solved by technology

This gets worse for fin transistors because the fin active area is very narrow

Images