Broadband passive linear equalizer circuit of high-speed serial interface receiving end
A technology of high-speed serial interface and equalizer circuit, which is applied in the direction of instrumentation and electrical digital data processing, etc. It can solve the problems that the bandwidth is difficult to meet the requirements of high-speed serial data transmission, the application limitation of passive linear equalizer circuit, etc., and achieve low power consumption. consumption, reduce the bit error rate, and achieve the effect of linear equalization
Active Publication Date: 2020-02-11
ETOWNIP MICROELECTRONICS BEIJING CO LTD
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Problems solved by technology
Passive linear equalizer circuits have the advantage of low power consumption, but the bandwidth of traditional passive linear equalizer circuits is difficult to meet the requirements of high-speed serial data transmission, which limits the application of passive linear equalizer circuits
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[0032] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0033] Such as figure 1 As shown, a broadband passive linear equalizer circuit at the receiving end of a high-speed serial interface, the equalizer circuit includes: sequentially connected differential signal input port INP / INN, parallel high-frequency signal equalization branch and low-frequency signal equalization branch, Summing circuit and differential signal output port OUTP / OUTN;
[0034] The high-frequency signal equalization branch is used for equalizing the high-frequency part of the input signal;
[0035] The low-frequency signal equalization branch is used to equalize the low-frequency part of the input signal;
[0036] The summation circuit is used for signal superposition of the two signals output by the high-frequency signal equalization branch and the low-frequency signal equalization branch.
[0037] The high-freque...
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The invention discloses a broadband passive linear equalizer circuit of a high-speed serial interface receiving end. The equalizer circuit comprises a differential signal input port INP / INN, a high-frequency signal equalization branch and a low-frequency signal equalization branch which are connected in parallel. A summing circuit and a differential signal output port OUTP / OUTN which are connectedin sequence. The high-frequency signal equalization branch is used for carrying out equalization processing on the high-frequency part of the input signal. The low-frequency signal equalization branch is used for carrying out equalization processing on the low-frequency part of the input signal; and the summing circuit is used for carrying out signal superposition on two paths of signals output by the high-frequency signal equalization branch and the low-frequency signal equalization branch. A low-frequency signal equalization branch and a high-frequency signal equalization branch are connected in parallel to perform equalization processing on a low-frequency part and a high-frequency part of an input signal respectively. The high-frequency signal equalization branch and the low-frequencysignal equalization branch are superposed by a summing circuit at an output end OUTP / OUTN to complete broadband equalization processing on the input signal.
Description
technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a broadband passive linear equalizer circuit at a receiving end of a high-speed serial interface. Background technique [0002] The transmission and reception channels of high-speed serial data will introduce many non-ideal factors in the signal transmission process, such as the inherent skin effect and dielectric loss of transmission media such as printed circuit board wiring, backplane wiring, and cables. The impact of these non-ideal factors will deteriorate with the increase of the serial data rate, causing the channel to exhibit low-pass characteristics in the frequency domain, attenuating the high frequency part of the serial data. In the time domain, it is manifested as inter-symbol interference (ISI, Inter-Symbol-Interference), which deteriorates the eye diagram performance of received serial data and increases the bit error rate BER of received data. For the...
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IPC IPC(8): G06F13/40
CPCG06F13/4072G06F2213/0002
Inventor 徐震吴汉明
Owner ETOWNIP MICROELECTRONICS BEIJING CO LTD