A Broadband Passive Linear Equalizer Circuit for High-Speed Serial Interface Receiver
A technology of high-speed serial interface and equalizer circuit, which is applied in the direction of instrumentation, electrical digital data processing, etc., can solve the problems of the application limitation of passive linear equalizer circuit, the bandwidth is difficult to meet the requirements of high-speed serial data transmission, etc., and achieve low power consumption. consumption, reduce the bit error rate, and eliminate the effect of intersymbol interference and jitter
Active Publication Date: 2021-05-28
ETOWNIP MICROELECTRONICS BEIJING CO LTD
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Problems solved by technology
Passive linear equalizer circuits have the advantage of low power consumption, but the bandwidth of traditional passive linear equalizer circuits is difficult to meet the requirements of high-speed serial data transmission, which limits the application of passive linear equalizer circuits
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[0032] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0033] Such as figure 1 As shown, a broadband passive linear equalizer circuit at the receiving end of a high-speed serial interface, the equalizer circuit includes: sequentially connected differential signal input port INP / INN, parallel high-frequency signal equalization branch and low-frequency signal equalization branch, Summing circuit and differential signal output port OUTP / OUTN;
[0034] The high-frequency signal equalization branch is used for equalizing the high-frequency part of the input signal;
[0035] The low-frequency signal equalization branch is used to equalize the low-frequency part of the input signal;
[0036] The summation circuit is used for signal superposition of the two signals output by the high-frequency signal equalization branch and the low-frequency signal equalization branch.
[0037] The high-freque...
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The invention discloses a broadband passive linear equalizer circuit at the receiving end of a high-speed serial interface. The equalizer circuit includes: differential signal input ports INP / INN connected in sequence, high-frequency signal equalization branches and low-frequency signal equalization branches connected in parallel , a summation circuit, and a differential signal output port OUTP / OUTN; the high-frequency signal equalization branch is used for equalizing the high-frequency part of the input signal; the low-frequency signal equalization branch is used for equalizing the low-frequency part of the input signal; The sum circuit is used for signal superposition of the two signals output by the high-frequency signal equalization branch and the low-frequency signal equalization branch. In the present invention, the low-frequency signal equalization branch and the high-frequency signal equalization branch are connected in parallel, and the low-frequency part and the high-frequency part of the input signal are respectively equalized. Superimposed by the summation circuit, the broadband equalization processing of the input signal is completed.
Description
technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a broadband passive linear equalizer circuit at a receiving end of a high-speed serial interface. Background technique [0002] The transmission and reception channels of high-speed serial data will introduce many non-ideal factors in the signal transmission process, such as the inherent skin effect and dielectric loss of transmission media such as printed circuit board wiring, backplane wiring, and cables. The impact of these non-ideal factors will deteriorate with the increase of the serial data rate, causing the channel to exhibit low-pass characteristics in the frequency domain, attenuating the high frequency part of the serial data. In the time domain, it is manifested as inter-symbol interference (ISI, Inter-Symbol-Interference), which deteriorates the eye diagram performance of received serial data and increases the bit error rate BER of received data. For the...
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IPC IPC(8): G06F13/40
CPCG06F13/4072G06F2213/0002
Inventor 徐震吴汉明
Owner ETOWNIP MICROELECTRONICS BEIJING CO LTD