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SRAM reading delay control circuit and SRAM

A delay control and circuit technology, applied in information storage, static memory, digital memory information and other directions, can solve the problems of SRAM read margin loss and chip yield reduction.

Active Publication Date: 2020-04-03
SPREADTRUM COMM (SHANGHAI) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In the process of realizing the present invention, the inventor found that: when VDDP is higher than VDDC, if the voltage difference between the two is too large, the loss of the read margin (read margin) of the SRAM will be too large, and the chip yield rate will be reduced. reduce

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  • SRAM reading delay control circuit and SRAM
  • SRAM reading delay control circuit and SRAM
  • SRAM reading delay control circuit and SRAM

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Embodiment Construction

[0025] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0026] refer to figure 2 and image 3 , it can be found that under the premise that the pull-down capability of the SRAM unit is fixed, the size of the read margin (read margin) designed by the SRAM is related to the read delay time △T (that is, the time difference between WL rising and SAE rising), △T The larger the value is, the larger t...

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Abstract

The invention provides an SRAM reading delay control circuit and an SRAM. The SRAM reading delay control circuit comprises a delay module, a power switch module and a switch control module; the delaymodule is connected to a first voltage domain power supply through the power switch module and used for generating reading delay time; the power switch module is controlled by the switch control module and is used for adjusting the voltage of the power supply end of the time delay module so as to adjust the reading delay time generated by the time delay module; and the switch control module is used for adjusting the driving capability of the power switch module. According to the invention, when the power supply voltage of the voltage domain where the induction amplifier is located is higher than the power supply voltage of the voltage domain where the storage array is located, the reading allowance of the SRAM is increased, and the chip yield of the SRAM is improved.

Description

technical field [0001] The invention relates to the technical field of SRAM memory, in particular to an SRAM reading delay control circuit and an SRAM. Background technique [0002] The most common SRAM storage unit is 6T unit, and its circuit structure is as follows: figure 1 shown. When the voltage of node N1 is high (power supply voltage VDD) and the voltage of node N0 is low (ground voltage VSS), the value stored in the SRAM 6T cell is called logic 1; otherwise, it is logic 0. When it is necessary to read the data stored in the SRAM 6T unit, assuming that the currently stored value is 1, the corresponding operation is: (1) charge BL and BLB to a high voltage (generally equal to the power supply voltage VDD); (2) charge the word Line (Word Line, WL) is charged to a high voltage (generally equal to the power supply voltage VDD), MPG1 and MPG0 are turned on; (3) Since the voltage of node N1 is high and the voltage of node N0 is low, BL will maintain the high voltage uncha...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/419
CPCG11C11/419
Inventor 王林
Owner SPREADTRUM COMM (SHANGHAI) CO LTD