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MRAM unit reading circuit and reading method, and STT-MRAM

A technology for reading circuits and reference cells, which is applied in the field of STT-MRAM, can solve the problems of small read margin, low resistance value ratio, and small read circuit window, and achieve the effect of increasing read margin and improving accuracy

Pending Publication Date: 2021-07-23
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the traditional MRAM is limited by the process, and the ratio of the resistance value of the high-resistance and low-resistance states of the array unit Tunneling Magneto-Resistance (TMR) is low, which causes the read circuit to distinguish between the two states The window of the traditional readout circuit is relatively small, and the reference unit of the traditional readout circuit is usually fixed (voltage or current) level, and the overall decision margin depends on the smaller side of the read 0 unit or the read 1 unit, which leads to the traditional MRAM read circuit always has the problem of small read margin

Method used

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  • MRAM unit reading circuit and reading method, and STT-MRAM
  • MRAM unit reading circuit and reading method, and STT-MRAM
  • MRAM unit reading circuit and reading method, and STT-MRAM

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Embodiment Construction

[0047] figure 1 The structure of the read amplification circuit of the MRAM bit cell in the prior art is shown. Such as figure 1 As shown, the MRAM unit includes a transistor M1 and a magnetic tunnel junction MTJ (Magnetic Tunnel Junction); the sense amplifier circuit of the MRAM unit includes a bias circuit (not shown in the figure), composed of the first PMOS transistor PM1 and the second A current mirror unit 12 composed of two PMOS transistors PM2, a voltage limiting unit 13 composed of a first NMOS transistor NM1 and a second NMOS transistor NM2, a reference unit 14 composed of a drive transistor M2 and a reference resistor Rref, and a sense amplifier 15.

[0048] In the read mode, when the relative magnetization direction of the MTJ junction of the MRAM cell is parallel, the MTJ junction exhibits a low-resistance state, and compared with the reference resistance of the reference cell with low resistance in the same parallel state, the resistance is small, that is, RMTJ ...

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PUM

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Abstract

The invention discloses an STT-MRAM, an STT-MRAM bit cell and an MRAM cell reading circuit. The MRAM cell reading circuit comprises: a sense amplifier which is suitable for respectively charging an array bit line of a selected MRAM cell and a reference bit line of a dynamic feedback reference unit to preset high levels when a pre-charging signal is received; and a dynamic feedback reference unit which is suitable for being converted from a preset first stage to a second stage when receiving a word line starting signal, so as to increase the voltage difference between the data point voltage output by the selected MRAM unit and the reference point voltage output by the MRAM unit by changing the reference current output on the reference bit line; The sense amplifier is also suitable for reading the data point voltage output by the selected MRAM unit and the reference point voltage output by the dynamic feedback reference unit, performing differential amplification on the data point voltage and the reference point voltage and then outputting a corresponding digital level. According to the scheme, the reading margin of the MRAM unit reading circuit can be increased.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an MRAM unit reading circuit and a reading method, and an STT-MRAM. Background technique [0002] Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) has the characteristics of high read and write speed, high density, low power consumption, long data storage time and long life, and has immeasurable broad prospects. What is more noteworthy is that STT-MRAM can be developed based on the existing CMOS manufacturing technology and process, and the difficulty of technical relay is relatively small, so that it can directly challenge the low cost of flash memory. [0003] Among them, the MRAM cell in STT-MRAM has resistance variability, so data information is stored through its different resistance states. [0004] However, the traditional MRAM is limited by the process, and the ratio of the resistance value of the high-resistance and low-resistance states of the array...

Claims

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Application Information

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IPC IPC(8): G11C11/16
CPCG11C11/165
Inventor 汪腾野王韬罗睿明
Owner SEMICON MFG INT (SHANGHAI) CORP