MRAM unit reading circuit and reading method, and STT-MRAM
A technology for reading circuits and reference cells, which is applied in the field of STT-MRAM, can solve the problems of small read margin, low resistance value ratio, and small read circuit window, and achieve the effect of increasing read margin and improving accuracy
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[0047] figure 1 The structure of the read amplification circuit of the MRAM bit cell in the prior art is shown. Such as figure 1 As shown, the MRAM unit includes a transistor M1 and a magnetic tunnel junction MTJ (Magnetic Tunnel Junction); the sense amplifier circuit of the MRAM unit includes a bias circuit (not shown in the figure), composed of the first PMOS transistor PM1 and the second A current mirror unit 12 composed of two PMOS transistors PM2, a voltage limiting unit 13 composed of a first NMOS transistor NM1 and a second NMOS transistor NM2, a reference unit 14 composed of a drive transistor M2 and a reference resistor Rref, and a sense amplifier 15.
[0048] In the read mode, when the relative magnetization direction of the MTJ junction of the MRAM cell is parallel, the MTJ junction exhibits a low-resistance state, and compared with the reference resistance of the reference cell with low resistance in the same parallel state, the resistance is small, that is, RMTJ ...
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