Method for simulating power failure of memory in FPGA

Abstract

The invention discloses a method for simulating power failure of a memory in an FPGA (Field Programmable Gate Array). The method comprises the following steps: 1) selecting an information memory in the FPGA to store information of the power failure memory; 2) when the power-down memory is in a power-down state, sending a power-down signal to reset the information memory to the power-down state; 3)when the power-down memory is in write operation, updating address state information in the information memory; and 4) when the address state information in the information memory is 1, reading datawritten last time, otherwise, reading random data or 0. According to the method for simulating the power failure of the memory in the FPGA, rich memory resources on the FPGA are used for replacing information storage of a register, so that resources are saved, and the requirement of a time sequence is better met; the randomized operation is carried out at the data reading end, so that the power failure behavior can be simulated more truly.

Description

technical field [0001] The invention relates to the technical field of integrated circuit verification, in particular to a method for simulating memory power-off in FPGA. Background technique [0002] With the continuous development of ASIC design technology, more and more ASIC designs in recent years have adopted multi-voltage domain design for digital circuits. The design of multiple voltage domains enables the digital part to better meet the requirements of low power consumption. It plays a pivotal role in the design of current handheld devices or wireless headsets that are extremely sensitive to power consumption. [0003] However, current FPGAs have limited support for multi-voltage domains in the digital part, and some manufacturers do not even support this aspect. Among supported manufacturers, the processing of memory power-off will take up a lot of logic resources and lead to poor timing. [0004] figure 2 It is a method for simulating memory power-down in the p...

AI Technical Summary

Problems solved by technology

Although on FPGA, register resources are relatively abundant, but such consumption will be quite tight; second, need to utilize figure 1 A very large mux shown on the left side of the figure performs multi-level selection. This kind of multi-channel selection to the Nth power of 2 will introduce a very large data path delay in timing, plus the delay of the memory itself, It will be very difficult in timing closure

Third, when the data that has not been rewritten is read after the power failure is restored, its value can only be 0, which is not enough to simulate the real state of the memory after power failure

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