Adaptive quality of service control circuit

Abstract

Disclosed approaches of controlling quality of service in servicing memory transactions includes periodically reading (206) by a quality of service management (QM) circuit (116), respective first datarate metrics and respective latency metrics from requester circuits (106, 108, 110, 112) while the requester circuits are actively transmitting memory transactions to a memory controller (104). The QM circuit periodically reads (208) a second data rate metric from the memory controller while the memory controller is processing the memory transactions, and determines (210), while the requester circuits are actively transmitting memory transactions to the memory controller, whether or not the respective first data rate metrics, respective latency metrics, and second data rate metric satisfy a quality of service metric. In response to determining that the operating metrics do not satisfy the quality of service metric, the QM circuit dynamically changes (212) value(s) of a control parameter(s) of the requester circuit(s) and of the memory controller.

Description

technical field [0001] The present invention generally relates to managing quality of service in processing storage transactions. Background technique [0002] A system on chip (SOC) typically includes components such as memory, one or more processors, and input / output (I / O) circuits fabricated on a single integrated circuit die. SOCs may also include programmable logic circuits, such as circuits formed on field programmable gate arrays (FPGAs). The SOC provides multiple configuration parameters for adjusting storage traffic and controlling Quality of Service (QOS). [0003] Quality of service during access to storage resources is usually measured in the form of latency and bandwidth utilization. Latency is the amount of time from when a requester issues a store transaction to when the requester receives data from a read transaction or acknowledges completion of a write transaction. Storage bandwidth refers to the theoretical or nominal rate (for example, bytes per second...

AI Technical Summary

Problems solved by technology

[0004] Due to the complexity and variability of SOC architectures and the large number of different applications that can be deployed on the SOC, it can be challenging to efficiently regulate the SOC's memory bandwidth allocation among multiple requestors and traffic types

In addition, the performance of a storage system is usually non-linear with respect to changes in a single control parameter among multiple control parameters, since multiple factors other than a single control parameter can affect performance

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