Time sequence optimization device for sensitive signal line of system-on-chip
A sensitive signal and optimization device technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve the problem of low timing optimization efficiency and achieve the effect of improving timing optimization efficiency
Active Publication Date: 2020-05-29
PHYTIUM TECH CO LTD
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[0004] The present invention provides a timing optimization device for sensitive signal lines of an on-chip system, the purpose of which is to solve the problem that the timing optimization process of the signal lines will have a negative impact on the surrounding paths that do not need to be optimized, resulting in low efficiency of timing optimization
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[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some of the embodiments of the present invention, but not all of them. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.
[0022] It should be noted that when an element is referred to as being “fixed” or “disposed on” another element, it may be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the oth...
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The invention provides a time sequence optimization device for a sensitive signal line of a system-on-chip, and the device comprises a power supply shielding line disposed around the sensitive signalline, and a power supply end of the power supply shielding line is connected with an output end of a power supply circuit of the system on chip, wherein the sensitive signal line is a signal line on atime sequence violation path when the system-on-chip performs static time sequence analysis. According to the invention, the propagation delay of the signal line can be controlled under the conditionof not influencing the periphery of the signal line and not needing an optimized path, the time sequence optimization of the signal line is completed, and the time sequence optimization efficiency ofthe system-on-chip is improved.
Description
technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a timing optimization device for sensitive signal lines of an on-chip system. Background technique [0002] In the physical design process of integrated circuit chips, one of the most important and necessary tasks after wiring is static timing analysis. Based on the results, the physical design should be optimized if timing violations occur. The delay in the design of the chip (that is, the system on a chip) is composed of two parts: the device delay and the interconnection line (ie, the signal line between the devices) delay. With the improvement of the manufacturing process, the scale and integration of the design become higher and higher, and the proportion of the delay of the interconnect line increases sharply and becomes the main part. [0003] After the traditional timing optimization method is implemented, local rewiring is required. After the timing converg...
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IPC IPC(8): G06F30/3312G06F30/392G06F115/06
Inventor 张弛张少华马卓李珊珊欧平丁军锋田金峰郭御风张明
Owner PHYTIUM TECH CO LTD