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Interactive ECO method for improving time sequences through adjusting clock tree branches

An interactive, clocking technology, applied in CAD circuit design, special data processing applications, instruments, etc., to improve the efficiency of timing optimization and facilitate changes

Active Publication Date: 2018-04-13
北京华大九天科技股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] In order to solve the deficiencies in the prior art, the object of the present invention is to provide an interactive ECO method for improving timing by adjusting clock tree branches. During automatic repair, according to the input timing report information and timing optimization goals, the timing improvement brought about by clock tree branch adjustment is estimated, and the appropriate clock is interactively selected by checking the cell position and the physical distribution of the line network on the chip layout Tree branch drive point, so as to achieve the purpose of adjusting clock path delay to improve timing

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  • Interactive ECO method for improving time sequences through adjusting clock tree branches
  • Interactive ECO method for improving time sequences through adjusting clock tree branches
  • Interactive ECO method for improving time sequences through adjusting clock tree branches

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Embodiment Construction

[0032] The preferred embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

[0033] figure 1 For the flow chart of the interactive ECO method for improving timing by adjusting clock tree branches according to the present invention, reference will be made below figure 1 , the interactive ECO method for improving timing by adjusting clock tree branches of the present invention is described in detail.

[0034] First, in step 101, a timing path report with timing violation is read. Among them, information such as all units, loads, and timings on the clock path and data path are included. The amount of timing change that may be caused by the forward or backward adjustment of the clock tree branch can be estimated through the timing incremental ...

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Abstract

The invention discloses an interactive ECO method for improving time sequences through adjusting clock tree branches. The method comprises the following steps of: reading a time sequence path report in which a synchronization unit is located and time sequence violation exists; estimating a to-be-adjusted series of a clock tree branch according to a given time sequence path report content; highlighting a position of the clock tree branch on a physical layout; and selecting a proper driving point according to a practical physical distribution condition so as to interactive clock tree branch adjustment. Through the interactive ECO method for improving time sequences through adjusting clock tree branches, time sequence improvement brought by clock tree branch adjustment is estimated accordingto input time sequence report information and a time sequence optimization target, and the proper clock tree branch driving point is interactively selected through a position of a check unit on a chiplayout and a physical distribution condition of a net, so that the aim of improving a time sequence through adjusting clock path delay is achieved.

Description

technical field [0001] The invention relates to the technical field of electronic design automation (EDA), in particular to an interactive ECO method for improving timing by adjusting clock tree branches. Background technique [0002] In the design process of integrated circuits, after the physical layout and routing steps, timing checks are required to ensure that the clock signal and data signal arrival time of the synchronous circuit meet the setup time (Setup Time) constraints and hold time (Hold Time) constraints. Require. [0003] build time T setup = delay data_path + library unit time setup - Deviation clock_path [0004] Hold time T hold = deviation clock_path + library unit time hold - Delay data_path [0005] If the setup time or hold time does not meet the constraints (that is, a timing violation occurs), ECO (Engineering Change Order) modification is required to meet the timing constraints to ensure the normal operation of the circuit. [0006] ...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/3312G06F30/39G06F2119/12
Inventor 陈彬董森华燕昭然刘毅
Owner 北京华大九天科技股份有限公司