A method and device for automatically grouping load units to repair timing violations
A load cell and timing technology, applied in special data processing applications, instruments, calculations, etc., can solve the problems of buffer cell insertion, waste of chip area, difficult ECO wiring operations, etc., to reduce the impact, reduce the number, and improve timing optimization. The effect of efficiency
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Embodiment 1
[0069] figure 2 is a schematic diagram of a net with a timing violation of hold time in one embodiment, such as figure 2 As shown, on a net in the design, the driver cell is connected to three load cells, and two load cells (V1 and V2) have a timing violation of the hold time (the timing violation value is -0.5).
[0070] image 3 Repair for traditional methods figure 2 Schematic diagram of timing violation of hold time in nets, such as image 3 As shown, using the conventional repair method, two buffer units (assuming one buffer unit can provide a delay of 0.25) are respectively inserted before timing violation units V1 and V2, and a total of four buffer units are inserted.
[0071] Figure 4 for repair according to the invention figure 2 Schematic diagram of timing violation of hold time in nets, such as Figure 4 As shown, using the timing violation method for repairing the holding time of the present invention, firstly, the timing violation units V1 and V2 are gr...
Embodiment 2
[0073] In the optimization process considering the insertion of buffer cells, the location distribution of cells in the physical layout must also be considered, so as to avoid grouping load cells with farther distances into the same group, resulting in excessive changes to the physical wiring. In general, the cluster diameter distance, D, is related to the cell rationalization placement constraints of the optimization algorithm (the range of positions that allow ECO cells to be placed).
[0074] Figure 5 A schematic diagram of repairing timing violations according to another embodiment of the present invention, such as Figure 5 As shown, starting from the timing violation unit, find close timing violation points within the cluster diameter distance D for clustering (such as unit 1 and unit 2, unit 3 and unit 4), and decide to insert the buffer according to the timing violation. the number of units. A total of five buffer units are inserted in this timing optimization, whil...
Embodiment 3
[0076] Image 6 According to the block diagram of the device for automatically grouping load cells to repair timing violations according to the present invention, such as Image 6 As shown, the device 60 for automatically grouping load cells to repair timing violations of the present invention includes a processor 601 and a memory 602, the memory 602 stores a program, and the program is read by the processor 601 When executed, do the following:
[0077] Read in a timing path report with a timing violation with hold time. This includes information on all units, loads, timing, and physical locations on the clock path and data path;
[0078] Identify the nets for timing repair. Find the drive unit of the net and each load unit that has a timing violation of the hold time;
[0079] Determine the maximum number N of candidate units that can be included in each knot group, and the diameter distance D of the knot group;
[0080] Analyze the timing violation and timing margin of ...
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