Stacked buck converters

[0050] In the following description, various specific details are shown in order to provide an in-depth understanding of the embodiments. The embodiments may be obtained without one or more specific details, or using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments are not obscured.

[0051] In the framework of this specification, references to "an embodiment" or "one embodiment" are intended to indicate that a specific configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in various places in this specification do not necessarily refer to the same embodiment. In addition, specific configurations, structures or features can be combined in any suitable manner in one or more embodiments.

[0052] The references used herein are provided for convenience only, and therefore do not limit the scope of protection or the scope of the embodiments.

[0053] in the following Figure 3 to Figure 15 In, already referenced Figure 1 to Figure 2 The described parts, elements, or components are designated by the same signs as those previously used in these figures; in order not to burden the detailed description, the description of these elements described above will not be repeated below.

[0054] image 3 A first embodiment of the electronic converter 1a according to the present description is shown. Also in this case, the electronic converter 1a includes:

[0055] -Two input terminals 10a and 10b, configured to receive DC input voltage V in;with

[0056] -Two output terminals 12a and 12b, configured to provide a DC output voltage V OUT.

[0057] In the considered embodiment, the negative output terminal 12b is connected (for example directly) to the negative input terminal 10b representing the ground GND. In the considered embodiment, the capacitor C OUT It is connected (for example directly) between the output terminals 12a and 12b.

[0058] In the considered embodiment, four electronic switches HS1, RST, HS2 and LS2 are (for example directly) connected in series between the input terminals 10a and 10b. For example, in the considered embodiment, the switches HS1, RST, HS2 and LS2 are FETs, preferably n-channel FETs, such as MOSFETs.

[0059] In particular, in the considered embodiment, the intermediate point between the switch HS1 and RST, for example the source terminal of the transistor HS1/the drain terminal of the transistor RST is via the capacitor C S And inductor L 1 It is connected (for example directly) to the output terminal 12a. In particular, the capacitor C S The first terminal is connected to the midpoint between switch HS1 and RST, and the capacitor C S The second terminal of is connected to terminal 12a through inductor L1. In addition, another electronic switch LS1 (for example, a FET, preferably an n-channel FET, such as a MOSFET) is also (for example directly) connected to the capacitor C S The second terminal (ie capacitor C S Between the midpoint between the inductor L1 and the negative input terminal 10b/ground GND.

[0060] In the considered embodiment, the intermediate point between the switches HS2 and LS2, for example the source terminal of the transistor HS2/the drain terminal of the transistor LS2, is connected (for example directly) via the inductor L2 to the output terminal 12a.

[0061] Finally, in the considered embodiment, the intermediate point between the switch RST and HS2, for example the source terminal of the transistor RST/the drain terminal of the transistor HS2 is via the capacitor C M It is connected (for example directly) to the negative input terminal 10b/ground GND.

[0062] therefore, image 3 The electronic converter 1a shown includes two step-down stages/phases:

[0063] -The first phase is represented by switches LS2, HS2 and inductor L2; and

[0064] -The second phase consists of switches HS1, LS1 and RST, capacitor C S And inductor L1.

[0065] In particular, with a series capacitor (by capacitor C S Said) compared to the traditional buck converter, image 3 The shown electronic converter 1a therefore includes electronic switches such as MOSFET, RST and capacitor/capacitor C M. As will be explained below, due to the existence of these two components, the two step-down phases may be completely independent, and the duty cycle is also greater than 50%. In addition, the inventor also noticed that the response of the system is essentially the equivalent response of a two-phase multi-phase buck. It can superimpose the conduction period of the switches HS1 and HS2 under the load transient condition to reduce The duty cycle increases to a value higher than 50%, which is not possible in the case of a conventional buck converter with series capacitors.

[0066] In the considered embodiment, the electronic switches HS1, LS1, RST, HS2, and LS2 therefore generate corresponding drive signals D HS1 , D LS1 , D RST , D HS2 And D LS2 The control circuit 14a is driven.

[0067] In particular, in various embodiments, the driving signal D for the switch RST RST With the drive signal D used to switch HS1 and LS1 HS1 , D LS1 In phase. Specifically, in various embodiments, the driving signal D for the switch LS1 LS1 Corresponds to the drive signal H for switch HS1 LS1 The inverted version of RST, and the drive signal D used to switch RST RST Corresponds to the drive signal D for switch LS1 LS1; That is, the control circuit 14a is configured to periodically repeat the following interval:

[0068] -In the first interval T ON1 During this period, switch HS1 is closed and switches LS1 and RST are opened; and

[0069] -In the second interval T OFF1 During this period, switch HS1 is opened and switches LS1 and RST are closed.

[0070] Therefore, in various embodiments, the switching period T for the switches HS1, LS1, and RST SW1 Is T SW1 = T ON1 +T OFF1; That is, the drive of the switch HS1 corresponds to the working ratio of T ON1 /T SW1 The pulse width modulation.

[0071] Similarly, make the drive signal D of the switches HS2 and LS2 HS2 , D LS2 Synchronous, and the drive signal D of switch LS2 LS2 Corresponding to the drive signal H of the switch HS2 LS2 That is, the control circuit 14a is configured to periodically repeat the following interval:

[0072] -In the first interval T ON2 During this period, switch HS2 is closed and switch LS2 is opened; and

[0073] -In the second interval T OFF2 During this period, switch HS2 is opened and switch LS2 is closed.

[0074] Therefore, in various embodiments, the switching period T of the switches HS2 and LS2 SW2 Is T SW2 = T ON1 +T OFF2; That is, the drive of the switch HS2 corresponds to the working ratio of T ON2 /T SW2 The pulse width modulation.

[0075] Generally speaking, the drive signal D HS2 , D LS2 No need to drive signal D HS1 , D LS1 And D RST Synchronize. However, for adjustment reasons, it may be preferable that the drive signal D HS2 With respect to drive signal D HS1 The constant phase P. Therefore, in this case, the switching period T SW1 Corresponding to switching period T SW2 , That is, T SW1 = T SW2.

[0076] In addition, in some embodiments, in order to make the cross capacitor C M The voltage V M The ripple on the above is minimized, preferably 50% interleaving between the two phases; that is, the control circuit 14a is configured to be substantially during the switching period T SW1 Start of (ie, time T from closing switch HS1) SW1 Switch HS2 is closed at /2. As mentioned earlier, this is unnecessary from the operational point of view of the topology, because it also causes the conduction periods of the two switches HS1 and HS2 to overlap, which is different from the mentioned prior art.

[0077] As will be explained in more detail below, by using the appropriate drive of the switches HS1, LS1, RST, HS2, and LS2, these switches are at V in /2 works under the maximum operating voltage. Therefore, a type of FET/MOSFET with a higher quality factor can be used to improve efficiency or double the switching frequency, and the output inductances L1 and L2 can be smaller, thereby increasing the power density of the battery.

[0078] Therefore, suppose the drive signal D HS1 And D HS2 The phase shift between P is 50%, and there are two driving scenarios:

[0079] -In the first case, when the duty cycle T ON1 /T SW1 When it is less than 50%, the switch HS2 is set to the closed state when the switch HS1 is opened;

[0080] -In the second case, when the duty cycle T ON1 /T SW1 When it is greater than 50%, the switch HS2 is set to a closed state when the switch HS2 is opened.

[0081] Figure 4 The first case is schematically shown, which shows the driving signals D for switches HS1, LS1, RST, HS2, and LS2 HS1 , D LS1 , D RST , D HS2 And D LS2 的实施例。 Example.

[0082] In particular, in the considered embodiment, the control circuit 14a is configured to:

[0083] -At time t1, switch HS1 is closed and switches LS1 and RST are opened;

[0084] -At time t2, switch HS1 is opened and switches LS1 and RST are closed;

[0085] -At time t3, switch HS2 is closed and switch LS2 is opened; and

[0086] -At time t4, switch HS1 is opened and switch LS2 is closed.

[0087] Therefore, during the first interval Δt1 (between time t1 and t2), the switches HS1 and LS2 are closed, and the switches LS1, RST, and HS2 are open. During the second interval Δt2 (between time t2 and t3), the switches LS1, RST, and LS2 are closed, and the switches HS1 and HS2 are open. During the third interval Δt3 (between time t3 and t4), the switches LS1, RST, and HS2 are closed, and the switches HS1 and LS2 are open. Finally, during the fourth interval Δt4 (between time t4 and the next time t1'), the switches LS1, RST, and LS2 are closed, and the switches HS1 and HS2 are open.

[0088] Therefore, in the considered embodiment, the time T of the switching period SW1 Corresponds to the sum of the duration of the four intervals, namely:

[0089] T SW1 = T SW2 =Δt1+Δt2+Δt3+Δt4.

[0090] In addition, the closing time T of switch HS1 ON1 Corresponds to time Δt1, namely T ON1 =Δt1, the closing time T of switch HS2 ON2 Corresponds to time Δt3, namely T ON2 =Δt3, and the phase shift P between switches HS1 and HS2 is P=(Δt1+Δt2)/T SW1.

[0091] Figure 5A The operation during the first interval Δt1 in this context is shown.

[0092] This step basically corresponds to the excitation step. In particular, if across capacitor C S Use V for the voltage S Means that the first terminal of inductor L1 (connected to capacitor C S Terminal) is equal to V in -V S (Switch HS1 is closed and switch LS1 is open). Conversely, the voltage on the second terminal of the inductor L1 corresponds to the voltage V OUT. In the considered embodiment, the voltage V in -V S -V OUT Therefore it is applied to the inductor L1. Therefore, since the voltage on the inductor L1 should be positive in this operation step, the current I1 through the inductor L1 increases, as occurs in a conventional buck converter.

[0093] Therefore, when the switch HS1 is set to the open state and the switch LS1 is set to the closed state, the first terminal of the inductor L1 (connected to the capacitor C S The terminal) is now connected to terminal 10b/ground GND. This is Figure 5B Also shown in. Therefore, in this operation step, the voltage on the inductor L1 is negative, and the current I1 through the inductor L1 decreases, as happens in a conventional buck converter.

[0094] However, as Figure 5B As shown, during the second operating interval Δt2, the switch RST is also closed. Therefore, the capacitor C S With capacitor C M Connected in parallel; that is, the capacitor transfers part of its charge to the capacitor C S And the voltage V M Increase the amount ΔV given by the following formula M1 :

[0095] ΔV M1 = T ON1 ·I1/(C S +C M )

[0096] Where T ON1 Corresponds to the duration Δt1, which is the on-time of the switch HS1.

[0097] Therefore, by using capacitor C M The switch RST in the converter stores the charge accumulated during the excitation period of the first phase (HS1, LS1, L1) of the converter. Therefore, stored in capacitor C M The charge in the converter can be used to provide energy for the second phase (HS2, LS2, L2) of the converter.

[0098] So like Figure 5C As shown, during the interval Δt3, the switch HS2 is closed and the switch LS1 is open. In this case, the first terminal of inductor L2 (connected to the terminal of switch HS2) is therefore connected to capacitor C M And C S (Switch HS2 and RST are closed), which is connected to voltage V M. Conversely, the voltage on the second terminal of the inductor L2 corresponds to the voltage V OUT. In the considered embodiment, the voltage V M -V OUT Therefore it is applied to the inductor L2. Therefore, since the voltage across the inductor L2 should be positive in this operation step, the current I2 through the inductor L2 increases, as occurs in a conventional buck converter.

[0099] Therefore, when the switch HS2 is set to the open state and the switch LS3 is set to the closed state, the first terminal of the inductor L2 (the terminal connected to the switch HS2) is now connected to the terminal 10b/ground GND. This is Figure 5D Also shown in. Therefore, in this operation step, the voltage on the inductor L2 is negative, and the current I2 through the inductor L2 is reduced, as happens in a conventional buck converter.

[0100] In particular, through the second phase of the converter (HS2, LS2, L2) from the capacitor C M The charge subtracted will produce a voltage ΔV M2 The change is given by the following formula:

[0101] ΔV M2 = T ON2 ·I2/(C S +C M ).

[0102] Conversely, when the operating ratio is longer than the phase shift P (for example, higher than 50%), the excitation of the first phase (HS1, LS1, and L1) and the superposition of the switches of the second phase (HS2, LS2, and L2) produce slightly different sequence.

[0103] In particular, such as Image 6 As shown, in various embodiments, the control circuit 14a is configured to:

[0104] -At time t5, switch HS1 is closed and switches LS1 and RST are opened;

[0105] -At time t6, switch HS2 is opened and switch LS2 is closed;

[0106] -At time t7, switch HS2 is closed and switch LS2 is opened; and

[0107] -At time t8, switch HS1 is opened and switches LS1 and RST are closed.

[0108] Therefore, during the first interval Δt5 (between time t5 and t6), the switches HS1 and HS2 are closed, and the switches LS1, RST, and LS2 are open. During the second interval Δt6 (between time t6 and t7), the switches HS1 and LS2 are closed, and the switches LS1, RST, and HS2 are open. During the third interval Δt7 (between time t7 and t8), the switches HS1 and HS2 are closed, and the switches LS1, RST, and LS2 are open. Finally, during the fourth interval Δt8 (between time t8 and the next time t5'), switches LS1, RST, and HS2 are closed, and switches HS1 and LS2 are open.

[0109] Therefore, in the considered embodiment, the time of the switching period corresponds to the sum of the duration of the four intervals, namely

[0110] T SW1 = T SW2 =Δt5+Δt6+Δt7+Δt8.

[0111] In addition, the closing time T of switch HS1 ON1 Corresponds to the sum of time Δt5, Δt6 and Δt7, namely T ON1 =Δt5+Δt6+Δt7, the closing time T of switch HS2 ON2 Corresponds to the sum of time Δt7, Δt8 and Δt5, namely T ON2 =Δt7+Δt8+Δt5, and the phase shift P between the switches HS1 and HS2 is P=(Δt5+Δt6)/T SW1.

[0112] Figure 7A The operation during the first interval Δt5 in this context is shown.

[0113] In particular, as described earlier, during this operation step, the switches HS1 and HS2 are closed, and the switches LS1, RST, and LS2 are open. This procedure is therefore unique, as it is not possible with solutions according to the prior art.

[0114] In particular, the first terminal of the inductor L1 (connected to the capacitor C S The voltage on the terminal) is again equal to V in -V S (Switch HS1 is closed and switch LS1 is open). In contrast, the voltage on the first terminal of the inductor L2 (the terminal connected to the switch HS2) is equal to V M (Switch HS2 is closed and switch RST is open). In any case, the voltage on the second terminal of the inductor L1 and the voltage on the second terminal of the inductor L2 correspond to the voltage V OUT. Therefore, due to the voltage V in -V S And V M Should be higher than voltage V OUT , The currents I1 and I2 increase.

[0115] Next, like Figure 7B As shown, the switch HS2 is set to the open state, and the switch LS2 is set to the closed state. Therefore, from time t6, the voltage on the first terminal of the inductor L2 (the terminal connected to the switch HS2) is equal to zero, and the current I2 decreases, while the current I1 of the first phase of the converter (HS1, LS1, and L1) Continue to increase.

[0116] Therefore, when the control circuit 14a opens the switch LS2 and closes the switch HS2, the above-mentioned operation step Δt6 ends at time t7. Therefore, this situation basically corresponds to the reference Figure 7A The situation described; that is, the current I2 in the capacitor L2 starts to increase, and the current I1 of the first phase of the converter (HS1, LS1, and L1) continues to increase.

[0117] Finally, such as Figure 7D As shown, at time t8, the control circuit 14a opens the switch HS1 and closes the switch LS1. Therefore, from time t8, the first terminal of inductor L1 (connected to capacitor C S The voltage on the terminal of) is equal to zero, and the current I1 decreases, while the current I1 of the second phase of the converter (HS2, LS2, and L2) continues to increase.

[0118] However, in this step, the switch RST is also set to the closed state; that is, the capacitor C S Part of the charge accumulated during other steps is transferred to capacitor C M On (see also Figure 5C description of).

[0119] Therefore, also in this case, the capacitor C is stored during the excitation of the first phase of the converter (HS1, LS1, and L1). S The charge in is transferred to capacitor C M And used by the second phase of the converter (HS2, LS2 and L2). Therefore, by making the on time T of the switches HS1 and HS2 ON1 And T ON2 Equal, the balance of current in inductors L1 and L2 is automatically obtained:

[0120] T ON1 ·I1=T ON2 ·I2

[0121] In fact, in T ON1 = T ON2 In the case of, the currents are also equal, that is, I1=I2.

[0122] Therefore, in various embodiments, the control circuit 14a is configured to have the same conduction time T ON1 = T ON2 And the same deadline T OFF1 = T OFF2 To drive the switches HS1 and HS2. In addition, in some embodiments, the control circuit 14a is configured to be based on the output voltage V OUT To adjust the duration T ON1 And/or T OFF1 , Thus changing the output voltage V OUT Adjust to the desired value. In this way, the current sharing correction of the controller 14a is not required.

[0123] For example, in various embodiments, the controller 14a is configured to set the constant time T SW1 Used for switching cycle and adjusting duration T ON1 , Making the output voltage V OUT Corresponds to the required value; that is, the controller 14a can implement PWM adjustment.

[0124] For example, for this purpose, the control circuit 14a may implement a regulator including at least one I (integral) component, such as a PI (proportional integral) regulator or a PID (proportional integral derivative) regulator.

[0125] Generally speaking, one or more comparators can also be used to obtain similar PWM regulation. These comparators are configured as:

[0126] -When the voltage V OUT Increase time T when lower than lower threshold ON1;as well as

[0127] -When the voltage V OUT Decrease time T above higher threshold ON1.

[0128] However, time T ON1 Variable and time T SW1 Constant regulation systems may have instability problems, especially during load transients, that is, when the load changes. In this case, the problem of current sharing between the phases of the converter may also occur.

[0129] Therefore, in various embodiments, the control circuit 14a is configured to use a constant on-time T ON1 = T ON2 , And the cut-off time T OFF1 = T OFF2 Is variable; that is, the control circuit 14a changes the switching cycle time T SW1 = T SW2. For example, for this purpose, one can refer to the document US 8963519 B2, which describes being configured for output voltage V OUT Change the switching period (1/T SW1 ) The frequency control circuit. Therefore, also in this case, the switch HS1 (and similarly, the switch HS2) is driven by using a PWM drive signal, where the on-time T ON Is constant, and the switching period T SW The duration is variable. For example, also for this purpose, a regulator with an I component, such as a PI or PID regulator, can be used.

[0130] In the previously described solution, the converter 1a therefore comprises two step-down stages, which are connected in series between the input terminals 10a and 10b. The inventor noticed that this configuration is in The output voltage V OUT very useful. In order to adjust the lower output voltage V OUT , You can set multiple step-down stages in series to make the input voltage of each step-down stage equal to V in /N, where N is the number of step-down stages connected in series.

[0131] In particular, by grouping components together, two buck levels can be defined. The first step-down stage (hereinafter referred to as "SPH" (stacked phase)) includes switches HS1, LS1 and RST and capacitor C S And inductor L1. In contrast, the second step-down stage (hereinafter referred to as "BPH" (buck phase)) includes switches HS2 and LS2 and inductor L2.

[0132] In particular, Figure 8 An embodiment of a stage SPH is shown, which enables a modular converter to be obtained.

[0133] In particular, in the considered embodiment, the module SPH includes four terminals 100, 102, 104 and 120. In particular, the two electronic switches HS1 and RST are connected in series (for example, directly connected) between the terminals 100 and 102. For example, in the considered embodiment, two n-channel FETs (such as MOSFETs) are used, where the drain terminal of transistor HS1 is connected (such as directly connected) to terminal 100, and the source terminal of transistor HS1 is connected (such as directly connected ) To the drain terminal of the transistor RST, and the source terminal of the transistor RST is connected (for example, directly connected) to the terminal 102. Capacitor C S The inductor L1 is connected in series (for example, directly connected) between the intermediate point between the switches HS1 and RST (for example, the source terminal of the switch HS1) and the terminal 120. Specifically, the capacitor C S The first terminal of is connected (for example, directly connected) to the switches HS1 and RST, and the second terminal of the capacitor CS is connected (for example, directly connected) to the terminal 120 through the inductor L1. Finally, in capacitor C S An electronic switch LS1 is connected between the intermediate point between the inductor L1 and the terminal 104. For example, in the considered embodiment, an n-channel FET (e.g. MOSFET) is used, where the drain terminal of the transistor LS1 is connected (e.g. directly connected) to the capacitor C S And the source terminal of the transistor LS1 is connected (for example, directly connected) to the terminal 104.

[0134] Therefore, reference image 3 , In the following cases, Figure 8 The module shown can be used for the first phase of the electronic converter 1a:

[0135] -Terminal 100 is connected to terminal 10a,

[0136] -Terminal 102 is connected to capacitor C M ,

[0137] -Terminal 104 is connected to terminal 10b, which is ground GND, and

[0138] -The terminal 120 is connected to the terminal 12a.

[0139] In the considered embodiment, the module SPH also includes an optional control circuit 140. For example, in various embodiments, the control circuit 140 is configured to drive the switches HS1, RST, and LS1 according to the PWM driving signal received on the other terminal PWM1. For example, the driving signal applied to the terminal PWM1 may correspond to the driving signal D of the switch HS1 HS1 , And the control circuit 140 can generate the driving signal D of the switches RST and LS1 by inverting the above-mentioned driving signal. RST And D LS1.

[0140] Generally speaking, for capacitor C S , The module SPH can also include a capacitor C M. For example, the capacitor C M It may be connected (for example, directly connected) between the terminals 102 and 104.

[0141] in contrast, Picture 9 An example of a stage BPH capable of obtaining a modular converter is shown.

[0142] In particular, in the considered embodiment, the module BPH includes three terminals 106, 108, and 122. In particular, two electronic switches HS2 and LS2 are connected in series (for example, directly connected) between the terminals 106 and 108. For example, in the considered embodiment, two n-channel FETs (e.g. MOSFETs) are used, where the drain terminal of transistor HS2 is connected (e.g. directly connected) to terminal 106 and the source terminal of transistor HS2 is connected (e.g. directly connected) ) To the drain terminal of the transistor LS2, and the source terminal of the transistor LS2 is connected (for example directly connected) to the terminal 108. The inductor L2 is connected (for example, directly connected) between the intermediate point between the switches HS2 and LS2 (for example, the source terminal of the switch HS1) and the terminal 122.

[0143] Therefore, reference image 3 , In the following cases, Picture 9 The module shown in can be used for the second phase of the electronic converter 1a:

[0144] -Terminal 106 is connected to capacitor C M ,

[0145] -Terminal 108 is connected to terminal 10b, which is ground GND, and

[0146] -The terminal 122 is connected to the terminal 12a.

[0147] In the considered embodiment, the module BPH also includes an optional control circuit 142. For example, in various embodiments, the control circuit 142 is configured to drive the switches HS2 and LS2 according to a PWM drive signal received on the other terminal PWM2. For example, the driving signal applied to the terminal PWM2 may correspond to the driving signal D of the switch HS2 HS2 , And the control circuit can generate the drive signal D of the switch LS2 by inverting the above drive signal LS2.

[0148] Therefore, in order to implement a multiphase converter, all but one step-down stage (the grounded one) will include the module SPH in order to scale the voltage at the input of each step-down stage. Only the last step-down stage that is grounded does not need to scale the voltage, so the simplified step-down stage BPH can be used to realize the above-mentioned step-down stage.

[0149] E.g, Figure 10A An embodiment of an electronic converter is shown that includes three step-down stages connected in series. Therefore, the converter includes two step-down SPH 1 And SPH 2 And a step-down BPH.

[0150] In particular, the step-down SPH 1 The terminal 100 is connected to the terminal 10a, the step-down SPH 1 The terminal 102 is connected to the step-down SPH 2 Terminal 100, step-down SPH 2 The terminal 102 of the buck stage BPH is connected to the terminal 106, and the terminal 108 of the buck stage BPH is connected to the terminal 10b. In addition, the step-down SPH 1 , SPH 2 And BPH terminals 120 and 122 are connected to terminal 12a, where capacitor C OUT Connected between output terminals 12a and 12b.

[0151] Two capacitors C are also shown in the considered embodiment M1 And C M2 , Where the first capacitor C M1 Connected to step-down SPH 1 Between the terminal 102 and the ground GND, the second capacitor C M2 Connected to step-down SPH 2 Between the terminal 102 and the ground GND.

[0152] Furthermore, in the embodiment under consideration, a control circuit 144 is shown, which is configured to generate an SPH applied to the buck stage 1 , SPH 2 And BPH terminal PWM1 and PWM2 drive signals. Therefore, in the considered embodiment, the control circuits 140, 142, and 142 implement the control circuit 14a.

[0153] For example, in the considered embodiment, the control circuit 144 generates three PWM signals: for the module SPH 1 APWM0, for module SPH 2 The APWM120 and the APWM240 for the module BPH.

[0154] E.g, Figure 10B Examples of signals APWM0, APWM120, and APWM240 are shown. Specifically, in the considered embodiment, the three signals APWM0, APWM120, and APWM240 correspond to having the same switching period T SW And the same on-time T ON (Ie the same working ratio) three PWM signals. However, the signals APWM0, APWM120, and APWM240 are phase-shifted from each other. For example, in the considered embodiment, the phase shift between the various signals is 120°.

[0155] in contrast, Figure 11A An embodiment of an electronic converter is shown that includes four step-down stages connected in series. Therefore, the converter includes three stages of SPH 1 , SPH 2 And SPH 3 , And a level BPH.

[0156] In particular, level SPH 1 The terminal 100 is connected to the terminal 10a, level SPH 1 The terminal 102 is connected to the level SPH 2 Terminal 100, grade SPH 2 The terminal 102 is connected to the level SPH 3 Terminal 100, grade SPH 3 The terminal 102 of is connected to the terminal 106 of the stage BPH, and the terminal 108 of the stage BPH is connected to the terminal 10b. In addition, SPH 1 , SPH 2 , SPH 3 And the terminals 120 and 122 of the BPH level are connected to the terminal 12a, wherein a capacitor C is connected between the output terminals 12a and 12b OUT.

[0157] Three capacitors C are also shown in the considered embodiment M1 , C M2 And C M3 , Where the first capacitor C M1 Connected between the terminal 102 of the stage SPH1 and the ground GND, the second capacitor C M2 Connected to SPH 2 Between the terminal 102 and the ground GND, the third capacitor C M3 It is connected between the terminal 102 of the stage SPH3 and the ground GND.

[0158] In the considered embodiment, the control circuit 144 is again shown, the control circuit 144 is configured to generate the application stage SPH 1 , SPH 2 , SPH 3 And BPH terminal PWM 1 And PWM 2 The drive signal. Specifically, in the considered embodiment, the control circuit 144 generates four PWM signals: for the module SPH 1 APWM0, for module SPH 2 APWM180, for module SPH 3 APWM90 and APWM270 for module BPH.

[0159] E.g, Figure 11B Examples of signals APWM0, APWM90, APWM180, and APWM270 are shown. Specifically, in the considered embodiment, the four signals APWM0, APWM90, APWM180, and APWM270 correspond to having the same switching period T SW And the same on-time T ON (Ie the same working ratio) PWM signal. However, the signals APWM0, APWM90, APWM180, and APWM270 are phase-shifted from each other. For example, in the considered embodiment, the phase shift between the various signals is 90°.

[0160] Such as Picture 12 As shown, the electronic converter 1a can thus comprise N stages connected in series, where the first N-1 stages are Figure 8 The SPH type shown, where each level of SPH has been associated with the corresponding capacitor C M1 ,..., C MN-1 , And the last level is Picture 9 BPH type shown.

[0161] In this context, for example, the control circuit 14a implemented with circuits 140, 142, and 144 can drive the corresponding stage with any phase shift.

[0162] To this end, the control circuit 14a can use a given period T SW And given on-time T ON The corresponding PWM drive signal D HS1 Drives the electronic switch HS1 of each stage/module SPH. For example, in the embodiment under consideration, the driver circuit 144 generates for this purpose the SPNH 1 ,..., SPH N-1 The corresponding drive signal APWM 1 ,..., APWM N-1. In addition, when the electronic switch HS 1 When closed, the control circuit 14a can open the electronic switches RST and LS1, when the electronic switch HS 1 When opened, the control circuit 14a can close the electronic switches RST and LS1. For example, for all switches using n-channel FETs, the control circuit 14a can generate and invert the signal D HS1 Corresponding drive signal D RST And D LS1.

[0163] In addition, the control circuit 14a may use a period T SW And on-time T ON The PWM drive signal DHS2 drives the electronic switch HS2 of the stage/module BPH. For example, in the considered embodiment, the drive circuit 144 used for this purpose generates the corresponding drive signal APWM for the stage BPH N. In addition, when the electronic switch HS2 is closed, the control circuit 14a can open the electronic switch LS2, and when the electronic switch HS2 is opened, the control circuit 14a can close the electronic switch LS2. For example, for all switches using n-channel FETs, the control circuit 14a can generate a signal D corresponding to the inversion HS2 The drive signal D LS2.

[0164] Finally, in various embodiments, the control circuit 14a is based on the output voltage V OUT Change on time T ON Or preferably change the time period T SW , Especially for the output voltage V OUT Adjust to the desired value.

[0165] As previously mentioned, the control circuit 14a can use any phase shift for each stage. For example, the user can select the PWM drive signal sequence (for example, the signal APWM according to the coupling between the circuit board, the output coil, or other factors). 1 ,..., APWM N ) Phase shift between. In fact, as mentioned earlier, the PWM drive signal of one stage can have any phase shift with respect to the PWM drive signal of the next or previous stage comprised between 0° and 360°.

[0166] In various embodiments, in order to increase the current carrying capacity of the system, multiple structures may be set in parallel, thereby creating a matrix structure.

[0167] E.g, Figure 13 A 2×2 configuration is shown. In particular, in this case, the first level ASPH of the SPH type (see Figure 8 ) And BPH-type first-stage ABPH (see Picture 9 ) Is connected in series between the input terminals 10a and 10b, the terminals 120 and 122 of the middle stage ASPH and ABPH are connected to the positive output terminal 12a, and the capacitor AC M Associated with the level ASPH, for example connected to the terminal 102 of the level ASPH, which in turn is connected to the terminal 106 of the level ABPH. In addition, the second stage BSPH of the SPH type and the second stage BBPH of the BPH type are connected in series between the input terminals 10a and 10b, wherein the terminals 120 and 122 of the stages BSPH and BBPH are also connected to the positive output terminal 12a, and the capacitor BC M Associated with the stage BSPH, for example connected to the terminal 102 of the stage BSPH, which in turn is connected to the terminal 106 of the stage BBPH.

[0168] In the considered embodiment, the control circuit 14a therefore generates drive signals for the switches of the various stages. For example, in the considered embodiment, the control circuit 144 generates the drive signal APWM for the stages ASPH and ABPH, respectively 1 And APWM 2 , And generate drive signal BPWM for stage BSPH and BBPH 1 And BPWM 2.

[0169] In various embodiments, the above driving signals have the same time period T SW The PWM signal. In addition, the drive signals of the stages in the same chain/column, such as stages ASPH and ABPH, have the same on-time T ON.

[0170] In various embodiments, for example, the phase shift between the drive signals APWM1, APWM2, BPWM1, and BPWM2 can be selected to minimize the capacitance AC M And BC M. For example, in various embodiments,

[0171] -Drive signal APWM 1 And drive signal BPWM 2 In phase; and

[0172] -Drive signal APWM 2 And drive signal BPWM 1 In phase, where the drive signal APWM 2 Preferably relative to the drive signal APWM 1 Phase shift 180°.

[0173] The inventor noticed that in this way, a current sharing operation can also be performed to make the power supply currents of the two columns equal.

[0174] In particular, for this purpose, the control circuit 144 can change the time T of each column ON. For example, in the case where the first column (ASPH and ABPH) carries more current, the control circuit 144 can reduce the time T of the column. ON And/or increase the time T of the second column (BSPH and BBPH) ON.

[0175] Such as Figure 14 As shown, the topology can therefore be extended to an N×M level structure.

[0176] Specifically, each of the M columns includes N stages connected in series, where:

[0177] -The first stage is the stage SPH, where the terminal 100 is connected to the positive input terminal 10a;

[0178] -The last stage is stage BPH, where terminal 106 is connected to terminal 102 of the previous stage SPH, and terminal 108 is connected to negative input terminal 10a; and

[0179] -The middle stage is all stages of SPH, where the terminal 100 is connected to the terminal 102 of the previous stage of SPH.

[0180] Then, all the columns are connected in parallel between the terminals 10a and 10b, and the terminals 120 of all stages SPH and the terminals 122 of all stages BPH are connected to the positive output terminal 12a, which in turn passes through one or more capacitors C OUT Connect to the negative output terminal 12b.

[0181] In the considered embodiment, the control circuit 14a can thus again generate the drive signal for the switch. For example, in the considered embodiment, the control circuit 144 generates all having the same time period T SW N×M PWM drive signals PWM 1,1 …PWM N,M.

[0182] However, the control circuit can change the conduction time T of each column ON To achieve current sharing correction. In particular, as mentioned before, at the same time T ON The possibility of driving each stage of the same column results in an automatic balance of the current within the cells of the same column. However, correcting the current imbalance between different columns may be beneficial to prevent reliability problems (for example, due to greater heating of the stage carrying more current), and in the worst case to prevent the core of the inductor from outputting Saturation. For this, any multiphase control of fixed frequency or variable frequency can be used. In fact, in general, all levels of SPH and BPH in a column can use the same time period T SW And the same on-time T ON The PWM drive signal.

[0183] In particular, in various embodiments, the control circuit 14a (for example, by using an appropriate configuration of the circuit 144) is configured to first adjust the period T SW To obtain the required output voltage V OUT. Next, the control circuit 14a detects whether the load remains stable, for example, because the control circuit 14a no longer changes the time period T SW. Then, when the load is stable, that is, when there is no transient, the control circuit 14a changes the conduction time T of each column ON To achieve current sharing correction.

[0184] E.g, Figure 15 Shows that it is configured to generate P drive signals PWM for P stages SPH and BPH 1 ,..., PWM P A possible embodiment of the control circuit 144. In various embodiments, the parameter P may be programmable. For example, refer to Figure 14 , The parameter P corresponds to N×M.

[0185] In the considered embodiment, the control circuit 144 includes a finite state machine 1440. Specifically, for example, the finite state machine 1440 implemented by using a digital circuit is configured to generate P clock signals CK with a lower frequency in response to the clock signal CLK. 1 ,..., CK P. Specifically, the circuit 1440 generates P clock signals CK with the same period 1 ,..., CK P , Thereby identifying the time period T SW. In various embodiments, the phase shift of each generated signal CK relative to the previous and next signal CK is ±360°/P. Therefore, by changing the frequency of the clock signal CLK, the period T can be changed for all driving signals. SW.

[0186] In this embodiment, the signal CK 1 ,..., CK P It is then provided to the selection circuit 1442, which divides the clock signal CK 1 ,..., CK P One of the PWM with each drive signal 1 ,..., PWM P Associated. For example, for this, for each signal PWM 1 ,..., PWM P , The circuit 1442 can receive the corresponding selection signal PH_SEL 1 ,..., PH_SEL P. Generally speaking, the circuit 1442 is purely optional because the signal CK 1 ,..., CK P To signal PWM 1 ,..., PWM P The allocation of can also be fixed at the hardware level.

[0187] Finally, the circuit 144 includes the circuit 1444, which is configured to change each signal PWM 1 ,..., PWM P On time T ON1 ,..., T ONP.

[0188] To this end, the circuit 1444 can receive data CS_SEL 1 ,..., CS_SEL P , Which converts each signal PWM 1 ,..., PWM P Associated with corresponding columns 1,..., M of the matrix of N×M levels (see also Figure 14 ). Generally speaking, this function of the circuit 1444 is purely optional, because the assignment of PWM1,..., PWMP to columns 1,..., M can also be fixed at the hardware level.

[0189] In addition, the circuit 1444 receives the current CS_COL identifying each column 1,..., M 1 ,..., CS_COL M The phase shift of the data. Therefore, the circuit 1444 can change the signal PWM 1 ,..., PWM P On time T ON1 ,..., T ONP , So that they belong to the same column (for example, by the signal CS_SEL 1 ,..., CS_SEL P Mark) all signals PWM 1 ,..., PWM P Have the same on time T ON , And the circuit is based on the data CS_COL 1 ,..., CS_COL M To change the duration.

[0190] Of course, without affecting the principle of the present invention, the details of the configuration and embodiments can be compared with the content described and illustrated by way of example only without departing from the scope of the present invention defined by the following claims. There is a big change.