A cache protection method and device based on dynamic mapping mechanism

Abstract

Embodiments of the present invention provide a cache protection method and device based on a dynamic mapping mechanism. The method includes: when a processor sends an instruction to request a read operation to the cache, caching the address and address table of data requested by the processor in the cache data Compare the cache addresses of the requested data to determine whether the address of the requested data hits an entry in the address table; if it hits, query the valid bit table corresponding to the entry to determine whether the entry is in a valid state, if so, from the Get the data row address corresponding to the requested data in the association table, and fetch the requested data from the data table; if the miss or hit table entry is invalid, the cache will send a missing signal, forcing the processor to get the request from the main memory The data corresponding to the read operation. The embodiment of the present invention balances the cache access time, avoids timing information from being used, and improves the security of the processor.

Description

technical field [0001] The invention belongs to the technical field of information security, and in particular relates to a cache protection method and device based on a dynamic mapping mechanism. Background technique [0002] Speculative execution of instructions improves processor performance and is widely used in modern processors. However, current research shows that through speculative execution, the processor exposes kernel data, resulting in data leakage. [0003] Spectre and Meltdown attacks pose serious security threats to processors. In a common Spectre attack case, it accesses the kernel space through malicious instructions, and then uses the data in the kernel space as an address reference to load the memory data at the corresponding address. In this process, since the load class instruction loads the memory data with the kernel data as the address, the cache will be replaced, and the cache line of the corresponding address will be loaded into the cache. Altho...

AI Technical Summary

Problems solved by technology

[0005] In order to overcome the problem of processor performance loss caused by the above-mentioned existing cache protection method or at least partially solve the above-mentioned problem, an embodiment of the present invention provides a cache protection method and device based on a dynamic mapping mechanism

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