Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

A method and device for wake-up from power

A power and wake-up source technology, applied in the field of power wake-up methods and devices, can solve problems such as complexity and uneconomical design

Active Publication Date: 2022-07-12
DATANG MICROELECTRONICS TECH CO LTD
View PDF8 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as a low-cost chiplet system, this design is too cost-effective and complex

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A method and device for wake-up from power
  • A method and device for wake-up from power
  • A method and device for wake-up from power

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0054] figure 1 A schematic diagram of a power wake-up method according to an embodiment of the present invention, such as figure 1 As shown, the power wake-up method in this embodiment includes:

[0055] S11. When receiving the power-off control signal of the internal power domain, latch the power-off control signal.

[0056] In an exemplary embodiment, after the power wake-up signal is generated, the power wake-up signal may be cleared by the power-off signal.

[0057] In an exemplary embodiment, the power-off control signal may be latched by the first latch.

[0058] S12. Generate a power-off signal according to the latched power-off control signal, so as to power off the internal power domain.

[0059] In an exemplary embodiment, the power-off signal output by the first latch may be delayed by a delay circuit.

[0060] S13. After receiving the external wake-up signal, generate a power wake-up signal according to the external wake-up signal.

[0061] In an exemplary em...

Embodiment 2

[0069] figure 2 It is a schematic diagram of a power wake-up circuit according to the second embodiment of the present invention. image 3 This is a waveform diagram of the power wake-up circuit according to the second embodiment of the present invention. like figure 2 As shown, it includes a cross-power domain signal latch circuit 1, a cross-power domain signal latch circuit 2, a wake-up source generation circuit, an edge wake-up control circuit, a rising edge detection circuit, a falling edge detection circuit, RC filter circuit, AND gate 1, AND gate 2, delay unit, etc.

[0070] Wherein, the cross-power domain signal latch circuit 1 may include an isolation circuit 1 , a level conversion 1 , and a latch 1 .

[0071] Control of the internal power domain The active shutdown signal of the internal power supply (ie, the power supply shutdown control signal above) is input to the isolation circuit 1 of the signal latch circuit 1 across the power domain, and after level conve...

Embodiment 3

[0087] Figure 5 It is a schematic diagram of the power wake-up device according to the third embodiment of the present invention, such as Figure 5 As shown, the power wake-up device of the third embodiment includes:

[0088] The power-off signal generating module is configured to latch the power-off control signal when receiving the power-off control signal of the internal power domain; and generate the power-off signal according to the latched power-off control signal, thereby powering down the internal power domain;

[0089] a power wake-up signal generating module, configured to generate a power wake-up signal according to the external wake-up signal after receiving the external wake-up signal;

[0090] The module for clearing the power off signal is used for clearing the power off signal through the power wake-up signal, so that the internal power domain is powered on.

[0091] In an exemplary embodiment, the power-off signal generating module includes a first latch f...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a power wake-up method. The method includes: when receiving a power-off control signal of an internal power supply domain, latching the power-off control signal; and generating the power-off control signal according to the latched power-off control signal. A power-off signal is used to power off the internal power domain; when an external wake-up signal is received, a power-on wake-up signal is generated according to the external wake-up signal; the power-off signal is cleared by the power wake-up signal, thereby enabling The internal power domain is powered up. The invention also discloses a power wake-up device. The method and device provided by the present invention can realize the function of automatically turning on the power after the power is turned off in a system with only one internal power supply.

Description

technical field [0001] The present invention relates to the field of electronics, and in particular, to a power wake-up method and device in the field of electronics. Background technique [0002] With the development of the Internet of Things, reducing the standby power consumption of the chip system has become a requirement. It is generally desirable that the system-on-chip be in a power-down mode when not in operation. The existing chip system usually has two internal power supplies, one is the main power supply when working, and the other is a small power supply that wakes up the circuit after the main power supply is turned off, so that the chip system can turn off its own power supply when it is powered on and needs to work. Turn on the power to meet the need for the power saving level to still be woken up. However, as a low-cost chiplet system, this design is too cost-effective and complicated. SUMMARY OF THE INVENTION [0003] The technical problem to be solved ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/3206
CPCG06F1/3206Y02D30/50
Inventor 刘蕊丽刘彦高洪福
Owner DATANG MICROELECTRONICS TECH CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products