Display panel

A display panel and display area technology, applied in static indicators, instruments, etc., can solve problems such as unfavorable panel narrow frame design, achieve the effect of solving bad display phenomenon, solving the problem of wide GOA area, and facilitating narrow frame design

Active Publication Date: 2020-07-24
SHENZHEN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present application provides a display panel, which can solve the technical problem that the GOA area of ​​the existing display panel is relatively wide, which is not conducive to the narrow frame design of the panel

Method used

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Experimental program
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Effect test

Embodiment 1

[0044] Please refer to figure 2 As shown in , it is a schematic structural diagram of the display panel provided in Embodiment 1 of the present application. It should be noted, figure 2 In order to facilitate the description, only the multi-level high-frequency clock signal lines in the GOA circuit area are shown. The GOA circuit area also includes other signal buses mentioned above. figure 2 not shown in.

[0045] In this embodiment, the GOA circuit area 20 is located at one side of the display area 10 of the display panel in the scanning line direction as an example for illustration. The display area 10 also includes a plurality of scan lines 7 arranged along the row direction and a plurality of data lines (not shown) arranged along the column direction, and one row of the pixel units 2 is correspondingly connected to one of the scan lines 7 .

[0046] The GOA circuit area 20 includes cascaded n-level GOA circuit units 3 and N high-frequency clock signal lines extendin...

Embodiment 2

[0071] Such as Figure 5 As shown in , it is a schematic structural diagram of the display panel provided in Embodiment 2 of the present application. The structure of the display panel in this embodiment is the same / similar to the display panel in the first embodiment above, the only difference is that the display panel in this embodiment is a dual-drive display panel, that is, the GOA circuit area 20 is located in the display panel when scanning The two sides of the display area 10 in the line direction. That is, the display panel includes two sets of GOA circuits, and each set of GOA circuits includes cascaded n-level GOA circuit units 3 and N high-frequency clock signal lines, and also includes the compensation unit group 6 . The two GOA circuit areas 20 both include the compensation unit group 6 , and the specific design of the compensation unit group 6 is consistent with the design in the first embodiment above, and will not be repeated here. Wherein, each level of GOA ...

Embodiment 3

[0074] Such as Figure 6 As shown in FIG. 2 , it is a schematic diagram of a partial structure of a display panel provided in Embodiment 3 of the present application. The structure of the display panel in this embodiment is the same / similar to the display panel in the first embodiment above, the only difference is that the winding method of the compensation unit 60 in this embodiment is a circuitous design, which can further increase the The length of the wiring of the compensation unit 60 and the times of crossing other high-frequency clock signal lines can further increase the compensation capability of the resistance and capacitance of the compensation unit 60 .

[0075] In the display panel of the present application, by setting the compensation unit in the GOA circuit area, the compensation unit can compensate the difference in resistance and capacitance between different clock signals, thereby solving bad display phenomena such as horizontal lines; and by setting the com...

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Abstract

The invention provides a display panel, which comprises a pixel unit located in a display area and a GOA circuit area located in a non-display area. The GOA circuit area comprises n stages of cascadedGOA circuit units and N high-frequency clock signal lines. Each stage of GOA circuit unit is electrically connected with one of the N high-frequency clock signal lines through a signal connecting line; the first high-frequency clock signal line to the Nth high-frequency clock signal line are sequentially arranged on one side of the display area from near to far; the display panel further comprises at least two compensation unit sets, the compensation unit sets are located in the area where the N high-frequency clock signal lines are located, and one compensation unit set comprises N-1 compensation units. And the first high-frequency clock signal line to the (N-1) th high-frequency clock signal line are electrically connected with the (N-1) th compensation units in a one-to-one correspondence manner. The compensation unit group is arranged in the area where the high-frequency clock signal line is located, so that the problem that the GOA area is wide is solved, and the narrow frame design of the panel is facilitated.

Description

technical field [0001] The present application relates to the field of display technology, and in particular to a display panel. Background technique [0002] The gate driver on array (Gate Driver On Array, GOA) technology is a technology that directly fabricates gate driver ICs (GateDriver ICs) on the array (Array) substrate instead of a driver chip made of an external silicon chip. The GOA circuit is manufactured on the substrate around the display area, which simplifies the manufacturing process of the display panel and saves the bonding process in the direction of the horizontal scanning line, which can increase the production capacity and reduce the product cost. At the same time, it can improve the integration of the display panel and make it more It is suitable for making display products with narrow frame or frameless, satisfying the visual pursuit of modern people. [0003] As the size and resolution of display panels continue to increase, especially in large-size ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G09G3/20
CPCG09G3/20G09G2310/0267G09G2320/0223G09G2300/0426G09G3/2003G09G3/3266G09G3/3674G09G2300/0408G09G2300/0876
Inventor 肖邦清
Owner SHENZHEN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
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