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A bit identification method, device, system and electronic device of i2c bus

An identification method and identification system technology, applied in the field of device, I2C bus bit identification method, system and electronic equipment, can solve the problems of clock line affecting in-position identification, whole frame receiving error, etc.

Active Publication Date: 2021-05-18
BEIJING RUNKE GENERAL TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the I2C bus is susceptible to external interference, and some burrs on the clock line will affect the bit recognition, and in severe cases, it will cause the entire frame to receive errors

Method used

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  • A bit identification method, device, system and electronic device of i2c bus
  • A bit identification method, device, system and electronic device of i2c bus

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Embodiment Construction

[0042] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0043] In the present invention, the term "comprising", "comprising" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, but also includes none. other elements specifically listed, or also include elements inherent in such a process, method, article, or apparatus. Without further limitations, an element defined by the phras...

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Abstract

The present invention provides a bit recognition method, device, system and electronic equipment of an I2C bus, which can restore the SCL waveform and the SDA waveform through voltage sampling, and further calculate the unit duration of the SDA waveform transmission of one bit according to the baud rate of the I2C bus, And in the process of bit timing according to the unit time length, the timing result is calibrated by using the rising edge of the clock line of the SCL waveform, and the calibrated timing result is the basis or basis for dividing the SDA waveform. The present invention combines the baud rate of the I2C bus with the rising edge of the clock line of the SCL waveform for bit recognition, which can reduce or even avoid frame reception errors caused by external interference on the I2C bus, and greatly improve the accuracy of I2C bus reception and stability.

Description

technical field [0001] The present invention relates to the technical field of communication, and more specifically, relates to a bit identification method, device, system and electronic equipment of an I2C bus. Background technique [0002] see figure 1 The physical topology of the I2C bus is shown. The I2C bus is very simple in physical connection, consisting of SDA signal line (serial data line), SCL signal line (serial clock line) and pull-up resistors. Its communication principle is to generate the signals required by the I2C bus protocol by controlling the high and low level timing of the SCL signal line and the SDA signal line to complete the data transmission. [0003] At present, the bit recognition method of the I2C bus mainly relies on the falling edge of the clock line to judge the bit time. However, the I2C bus is susceptible to external interference, and some burrs on the clock line will affect the bit recognition, and in severe cases, it will cause the enti...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/42
Inventor 刘晨
Owner BEIJING RUNKE GENERAL TECH
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