A kind of semi-floating gate memory and its preparation method

Abstract

The invention discloses a semi-floating gate memory and a preparation method thereof. The semi-floating gate memory includes: a semiconductor substrate, which has a first doping type; a semi-floating gate well region, which has a second doping type, located in the upper region of the semiconductor substrate; a U-shaped groove, which runs through the semi-floating gate well region, the bottom of which is at the lower boundary of the semi-floating gate well region; the first gate dielectric layer covers the surface of the U-shaped groove; the floating gate covers the first gate dielectric layer and forms a raised shape with a high middle and low sides; tunneling transistor The channel layer covers the raised upper surface in the middle of the floating gate; the second gate dielectric layer is formed on both sides of the channel layer of the tunneling transistor and extends to cover the surface of the floating gate, and the control gate covers the second gate dielectric layer and the channel layer of the tunneling transistor upper surface; gate spacer, located on both sides of the first gate stack and the second gate stack; source and drain, formed in the semi-floating gate well region, located on the first gate stack and the second on both sides of the gate stack.

Description

technical field [0001] The present invention relates to the technical field of integrated circuit memory, in particular to a semi-floating gate memory and a preparation method thereof. Background technique [0002] At present, DRAM devices used in integrated circuit chips are mainly 1T1C structures, that is, a transistor is connected in series with a capacitor, and the capacitor is charged and discharged through the switch of the transistor, thereby realizing the conversion between DRAM devices 0 and 1. As the device size becomes smaller and smaller, DRAM devices used in integrated circuit chips are facing more and more problems. For example, DRAM devices require 64ms to refresh once, so the capacitance value of the capacitor must be kept above a certain value to ensure sufficient Long charge retention time. However, as the feature size of integrated circuits shrinks, the manufacture of large capacitors has become more and more difficult, and already accounts for more than ...

AI Technical Summary

Problems solved by technology

However, in the existing planar semi-floating gate memory devices, the tunneling transistor is located between the floating gate and the drain, which means that the tunneling transistor needs to occupy an additional part of the chip area, which will reduce the integration density of the chip

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