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Hybrid logical to physical caching scheme

A cache, physical address technology, applied in the field of memory devices, can solve problems such as increased processing time and a large amount of RAM storage space

Pending Publication Date: 2020-08-14
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In managed NAND environments such as UFS and eMMC, using this mapping can involve using large amounts of RAM storage space and increasing processing time, cost, and power consumption

Method used

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  • Hybrid logical to physical caching scheme
  • Hybrid logical to physical caching scheme
  • Hybrid logical to physical caching scheme

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Embodiment Construction

[0028] The following detailed description refers to the accompanying drawings, which show, by way of illustration and not limitation, various embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice these and other embodiments. Other embodiments may be utilized and structural, logical, mechanical, and electrical changes may be made to these embodiments. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. Accordingly, the following detailed description should not be viewed in a limiting sense.

[0029] The memory system can be configured to maintain a set of L2P pointers. L2P pointers relate physical addresses at a memory array of a memory system to logical addresses used by one or more hosts. The L2P pointer can be stored in RAM of the memory system. Read and write request...

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Abstract

The invention relates to hybrid logical to physical caching scheme. A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.

Description

[0001] priority application [0002] This application claims priority to U.S. Provisional Application No. 62 / 787,043, filed December 31, 2018, and U.S. Application No. 16 / 294,427, filed March 6, 2019, which are hereby incorporated by reference in their entirety . technical field [0003] The present invention relates to memory devices, and in particular to hybrid logical-to-physical caching schemes. Background technique [0004] Memory devices are typically provided as internal semiconductor integrated circuits in a computer or other electronic device. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data, and examples of volatile memory include random-access memory (RAM), dynamic random-access memory (DRAM), and synchronous dynamic random-access memory (DRAM). Access memory (synchronous dynamic random-access memory, SDRAM) and so on. Nonvolatile memory can retain stored data when power ...

Claims

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Application Information

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IPC IPC(8): G06F12/0873G06F12/02G06F12/1009
CPCG06F12/0873G06F12/0246G06F12/1009G06F2212/7201G06F2212/1016G06F2212/1044G06F12/0868G06F2212/466G06F12/0897
Inventor C·曼加内利Y·温博格A·萨萨拉P·帕帕L·埃斯波西托G·德利赛奥A·德拉莫妮卡M·亚库洛
Owner MICRON TECH INC
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