Three-dimensional memory device and method for forming the same
A three-dimensional storage and device technology, which is applied to semiconductor devices, electrical solid-state devices, electrical components, etc., can solve the problem that the top selective gate isolation structure and the bottom selective gate isolation structure cannot be introduced at the same time, and achieve the effect of improving device performance.
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Embodiment 1
[0086] see Figure 1 to Figure 3 , the present embodiment provides a three-dimensional memory device, characterized in that: comprising:
[0087] a base 100, which has an upper surface and a lower surface oppositely arranged;
[0088] The stacked structure 101, which is formed on the upper surface of the substrate 100, is formed by alternately stacking gate layers 102 and isolation layers 103; the stacked structure 101 includes a core area 104 and a stepped area with a stepped structure located around the core area 104 105;
[0089] A plurality of gate line gaps 106 are arranged at intervals in the stack structure 101 to divide the stack structure 101 into a plurality of memory blocks 107, and further divide the plurality of memory blocks 107 into a plurality of strip-shaped fingers storage area 108;
[0090] a plurality of channel structures 109, which are formed in the stacked structure 101, are located between adjacent gate line gaps 106, and penetrate through the stacke...
Embodiment 2
[0103] see Figure 4, this embodiment provides a three-dimensional memory device. Compared with the solution in the first embodiment that a storage block includes four finger storage areas and six bottom selection gate regions, the difference of this embodiment is that a storage block includes three finger storage areas 208 and six bottom selection gate areas Partition 213. In addition, compared to Example 1 figure 2 As shown, the step area 105 is located on the right side of the core area 104, Figure 4 The step area 205 is located on the left side of the core area 204 . Figure 4 The channel structure 209 located in the finger storage area 208 is also indicated in . Same as the first embodiment, the step region 205 can be further divided into a top selection gate region 205a, a core subregion 205b and a bottom selection gate region 205c. The top selection gate sub-region 205 a is connected to the top selection gate word line contact structure 215 , and the bottom selec...
Embodiment 3
[0107] see Figure 1 to Figure 9 , the present embodiment provides a method for forming a three-dimensional memory device, characterized in that: comprising the following steps:
[0108] Step 1), such as image 3 As shown, a substrate 100 is provided, and the substrate 100 has an upper surface and a lower surface oppositely arranged;
[0109] Step 2), such as Figure 1 to Figure 3 As shown, a stacked structure 101 consisting of gate layers 102 and isolation layers 103 is formed on the upper surface of the substrate 100; at least one layer of the gate layer 102 at the bottom of the stacked structure 101 constitutes a bottom selection gate 110; the bottom selection gate 110 is further formed with a bottom selection gate isolation structure 112 that divides the bottom selection gate 110 into a plurality of strip-shaped bottom selection gate regions 113; the stack structure 101 includes a core region 104 and a A stepped area 105 with a stepped structure around the core area 104...
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