Chip power supply network structure based on bridging mode

Abstract

The embodiment of the invention discloses a chip power supply network structure based on a bridging mode. According to the technical scheme provided by the embodiment of the invention, high-layer VDDstrip lines are connected with bridging VDD strip lines in a bridging metal layer through first via holes, and the bridging VDD strip lines and bottom-layer VDD strip lines are connected through second via holes, so that bridging between the high-layer VDD strip lines and the bottom-layer VDD strip lines is realized; high-layer VSS strip lines and bottom-layer VSS strip lines are connected throughthird via holes; signal lines can be arranged on the high-layer metal layer, the bridging metal layer, the winding metal layer and the bottom-layer metal layer, and the winding metal layer is not provided with a via hole at the position corresponding to the high-layer VDD strip lines; and the signal lines can be freely wound at the positions, corresponding to the high-layer VDD strip lines, of the winding metal layer under the condition that DRC rules are met, so that the situation of chip winding resource shortage is relieved, and the winding success rate is improved.

Description

technical field [0001] The embodiments of the present application relate to the field of chip technology, and in particular, to a bridge-based chip power network structure. Background technique [0002] Power supply planning is a key step in the physical design of the chip. Its goal is to design a uniform network for the power supply of the entire chip, so that power can be sent to each basic unit of the chip, so that the chip can work normally. With the continuous development of the chip manufacturing process, the feature size is continuously reduced and the clock frequency is continuously increased, which brings about the improvement of chip performance, while the scale continues to increase, and the complexity of the physical design also increases. [0003] The traditional power supply network is composed of criss-crossing power supply lines. The standard unit of the chip is generally connected to the low-level power supply line through the power supply PIN, and then conn...

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Problems solved by technology

[0004] In the existing traditional power supply planning scheme, in the area where vias are placed between the low-level and high-level power lines, the vias of the middle layers need to be connected layer by layer to complete the connection between the low-level and high-level power lines. In order to reduce short-circuit For DRC (DesignRuleCheck, design rule check) problems, the signal lines of each layer must not be routed through this area, resulting in tight chip routing resources

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