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One-bit full adder based on three-input FET device

A three-input, full adder technology, used in instruments, digital data processing components, logic circuits with logic functions, etc., can solve the problem of large circuit area, power consumption and power consumption delay product, complex circuit structure, CMOS Problems such as the number of transistors

Pending Publication Date: 2020-08-28
NINGBO UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The one-bit full adder uses a large number of CMOS transistors, the circuit structure is relatively complex, and the circuit area, power consumption and power consumption delay product are relatively large

Method used

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  • One-bit full adder based on three-input FET device
  • One-bit full adder based on three-input FET device
  • One-bit full adder based on three-input FET device

Examples

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Embodiment

[0011] Example: such as figure 2 As shown, a one-bit full adder based on three-input FET devices includes a first FET tube M1, a second FET tube M2, a third FET tube M3, a fourth FET tube M4, a fifth FET tube M5, a sixth FET tube FET tube M6, seventh FET tube M7, eighth FET tube M8, ninth FET tube M9, tenth FET tube M10, eleventh FET tube M11, twelfth FET tube M12, thirteenth FET tube M13 and Fourteen FET tubes M14, the first FET tube M1, the third FET tube M3, the fifth FET tube M5, the seventh FET tube M7, the ninth FET tube M9, the eleventh FET tube M11 and the thirteenth FET tube M13 respectively It is realized by using P-type three-input FET devices, the second FET tube M2, the fourth FET tube M4, the sixth FET tube M6, the eighth FET tube M8, the tenth FET tube M10, the twelfth FET tube M12 and the fourteenth FET tube The tube M14 is implemented by using N-type three-input FET devices respectively. The N-type three-input FET device has a first gate, a second gate, a th...

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Abstract

The invention discloses a one-bit full adder based on a three-input FET device. The one-bit full adder comprises a fourteenth FET, wherein seven FETs are realized by adopting a P-type three-input FETdevice, and other seven FETs are realized by adopting an N-type three-input FET device; when any two or three accessed input signals in three gates of the N-type three-input FET device are 1, a sourceelectrode and a drain electrode of the N-type three-input FET device are conducted; and a source electrode and a drain electrode of the P-type three-input FET device are conducted when any two or three accessed input signals in three gate electrodes of the P-type three-input FET device are 0. The one-bit full adder has the advantages that the circuit structure is simple, and the circuit area, thecircuit power consumption and the power consumption delay product are small.

Description

technical field [0001] The invention relates to a one-bit full adder, in particular to a one-bit full adder based on three-input FET devices. Background technique [0002] Since the short-channel effect seriously restricts the further reduction of the size of planar MOS devices, in order to continue Moore's Law, many ideas about new device structures have been proposed. Among them, due to its three-dimensional structure, FinFET improves the control ability of the gate to the channel, suppresses the short channel effect, reduces the leakage current of the device, and increases the on-state current. Existing studies have shown that when designing circuits, devices in the form of two inputs are more flexible and efficient than devices in the form of single inputs. The low-threshold two-input FinFET device is equivalent to two parallel transistors, and the high-threshold two-input FinFET device is equivalent to two series-connected transistors, which can simplify the circuit st...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/20G06F7/501
CPCH03K19/20G06F7/501
Inventor 胡建平戴凯陈泽奇叶浩
Owner NINGBO UNIV
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