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Interface circuit based on JESD204B protocol

A technology of interface circuits and protocols, applied in the field of high-speed serial interface circuits, can solve problems such as increasing design costs, and achieve the effects of simplified design, flexible application, and simple mechanism

Pending Publication Date: 2020-09-01
NANJING UNIV OF SCI & TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, at present, the JESD204B protocol transmission solution is mainly in the hands of foreign manufacturers,

Method used

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  • Interface circuit based on JESD204B protocol
  • Interface circuit based on JESD204B protocol
  • Interface circuit based on JESD204B protocol

Examples

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[0022] The interface circuit of the present invention is composed of a GTX interface circuit, a CGS detection circuit, an ILAS detection circuit, a data replacement circuit and a channel synchronization circuit; the GTX interface circuit uses the IP core to call N high-speed transceivers in the FPGA to realize the connection of N pairs of differential signal lines In, the serial data based on the JESD204B protocol is converted into parallel data, and the data and K code indication signal are output to the CGS detection circuit; the CGS detection circuit judges whether there is continuous 4 in each channel according to the input data and K code indication signal A K code (0xBC), after N channels are successfully detected, the Sync signal (link synchronization signal) output to the peripheral will be pulled high, and the data of each channel and K code indicator signal will be output to the ILAS detection circuit, waiting for the peripheral to send ILAS sequence. In addition, the ...

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Abstract

The invention discloses an interface circuit based on a JESD204B protocol. The interface circuit is composed of a GTX interface circuit, a CGS detection circuit, an ILAS detection circuit, a data replacement circuit and a channel synchronization circuit. Multi-channel data receiving can be achieved, data synchronization of all channels, the number of the channels, the channel rate and the like canbe programmed, and high flexibility and adaptability are achieved.

Description

technical field [0001] The invention belongs to the field of high-speed serial interface circuits, in particular to an interface circuit capable of realizing a high-speed AD sampling data serial transmission protocol—JESD204B protocol. Background technique [0002] With the continuous development of software radio technology, the application range of high-speed AD is more and more extensive, and the data interface speed of the digital terminal will become faster and faster. Traditional parallel transmission interfaces such as LVDS and CMOS have certain deficiencies in data interface speed, layout area, and timing processing. [0003] Compared with the traditional parallel data bus, the JESD204B high-speed serial interface has the following advantages: [0004] 1) The transmission rate is fast, and the single-channel transmission data rate can reach 12.5Gb / s; [0005] 2) The PCB design is simple, avoiding the length matching of parallel data lines such as LVDS and CMOS on t...

Claims

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Application Information

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IPC IPC(8): G06F13/40G06F13/42
CPCG06F13/4018G06F13/4204G06F2213/0012Y02D10/00
Inventor 张佳怡林舒情李洪涛
Owner NANJING UNIV OF SCI & TECH
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